You could use if else if statements to do this in verilog.
if(sci_read==1'b0)
begin
dbus = 8'bzzzzzzzz;
end
else if(addr==2'b0)
begin
dbus = rdr;
end
else if(addr==2'b0)
begin
dbus = scsr;
end
else begin
dbus = sccr;
end
My DBUS is an "inout" port hence by default it is of the type net. I cannot use it inside the always@() block. Hence no if else statements. Tell other way.