Help me convert this code from VHDL to Verilog

[brain123]

Doubt in verilog

Can u help me with this code.
This is a code in vhdl i want to convert into verilog.

info: dbus (8 bit inout data bus)
sci_read (1 bit conrol signal)
addr ( 2 bit addr bus)
rdr, sccr, scsr (internal 8 bit data reg)

VHDL code:
dbus <= (others = 'Z') when sci_read = '0',
else rdr when addr = "00",
else scsr when addr = "01",
else sccr;

Help me convert it into verilog.

 

[kaushiksangam]

Re: Doubt in verilog

You could use if else if statements to do this in verilog.

if(sci_read==1'b0)
begin
dbus = 8'bzzzzzzzz;
end
else if(addr==2'b0)
begin
dbus = rdr;
end
else if(addr==2'b0)
begin
dbus = scsr;
end
else begin
dbus = sccr;
end

 

[brain123]

Re: Doubt in verilog

My DBUS is an "inout" port hence by default it is of the type net. I cannot use it inside the always@() block. Hence no if else statements. Tell other way.

 

[tkbits]

Doubt in verilog

assign dbus =
  (sci_read==1'b0) ? 8'bzzzzzzzz :
  (addr==2'b0) ?     rdr :
  (addr==2'b1) ?     scsr :
                     sccr ;