Mar 6, 2012 #1 U uselessmail Junior Member level 3 Joined Mar 6, 2012 Messages 28 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,479 Hi there! Could someone help me convert this Verilog line into VHDL... Code: output reg outp; always @(posedge clk) {outp, data_out[7:1]} <= data_out[7:0]; Would really appreciate some help! Thanks!
Hi there! Could someone help me convert this Verilog line into VHDL... Code: output reg outp; always @(posedge clk) {outp, data_out[7:1]} <= data_out[7:0]; Would really appreciate some help! Thanks!
Mar 6, 2012 #2 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 Re: Verilog to VHDL help Code VHDL - [expand]1 2 3 4 5 6 7 process(clk) begin if rising_edge(clk) then output <= data_out(7); data_out(7 downto 1) <= data_out(6 downto 0); end if; end process;
Re: Verilog to VHDL help Code VHDL - [expand]1 2 3 4 5 6 7 process(clk) begin if rising_edge(clk) then output <= data_out(7); data_out(7 downto 1) <= data_out(6 downto 0); end if; end process;
Mar 6, 2012 #3 U uselessmail Junior Member level 3 Joined Mar 6, 2012 Messages 28 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,479 Re: Verilog to VHDL help Thanks a lot mate!