[SOLVED] Help me convert simple Verilog line to VHDL

[uselessmail]

Hi there! Could someone help me convert this Verilog line into VHDL...

output reg outp;
always @(posedge clk)
{outp, data_out[7:1]} <= data_out[7:0];

Would really appreciate some help!
Thanks!

 

[TrickyDicky]

Re: Verilog to VHDL help

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Code VHDL - [expand]
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process(clk)
begin
  if rising_edge(clk) then
    output <= data_out(7);
    data_out(7 downto 1) <= data_out(6 downto 0);
  end if;
end process;

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[uselessmail]

Re: Verilog to VHDL help

Thanks a lot mate!