shaiko
Advanced Member level 5
I need to analyze the following Vrilog code...
A few questions:
1. What is the purpose of rx1,rx2,rx3,rx4,rx5,rx6,rx7,rx8,rx_dly,idle ? Why are they parameterized ?
2. As I see : "tsclk0_sampled2" is sampled using the "OSC_CLK" signal. However, it's also used in the second "always" under the "negedge" statement. this will yield a gated clock - correct ?
Code:
module SPORT_BUS(
OSC_CLK,
TSCLK0, //4MHz DSP clk
TFS0, //DSP stobe
DT0PRI, //DSP Serial data input
REC_DATA, //8bit receive data buffer
RSCLK0, //4MHz FPGA clk
RFS0, //FPGA storbe
DR0PRI, //FPGA Serail data output
TR_DATA, //8bit transmit data buffer
RESET, //global reset
START, //start tx
NEW_REC, //New data is ready
READY
);
input OSC_CLK;
input TSCLK0;
input TFS0;
input DT0PRI;
input RESET;
input START;
input [7:0] TR_DATA;
output RSCLK0;
output RFS0;
output DR0PRI;
output NEW_REC;
output [7:0] REC_DATA;
output READY;
wire OSC_CLK;
wire TSCLK0;
wire TFS0;
wire DT0PRI;
wire RESET;
wire RSCLK0;
wire RFS0;
wire START;
wire NEW_REC;
wire [7:0] TR_DATA;
reg [7:0] REC_DATA;
reg [13:0] state1;
reg [13:0] state2;
reg DR0PRI;
reg READY;
reg tsclk0_sampled2;
reg tsclk0_sampled;
//assign RSCLK0 = TSCLK0;
assign RSCLK0 = tsclk0_sampled;
// s
// t
// r--1hot--43210;
parameter idle = 14'b00000000000000;
parameter tx1 = 14'b11000000000010;
parameter tx2 = 14'b00100000000011;
parameter tx3 = 14'b00010000000100;
parameter tx4 = 14'b00001000000101;
parameter tx5 = 14'b00000100000110;
parameter tx6 = 14'b00000010000111;
parameter tx7 = 14'b00000001001000;
parameter tx8 = 14'b00000000101001;
parameter rx_dly = 14'b00000000010011;
parameter rx1 = 14'b01000000001010;
parameter rx2 = 14'b00100000001011;
parameter rx3 = 14'b00010000001100;
parameter rx4 = 14'b00001000001101;
parameter rx5 = 14'b00000100001110;
parameter rx6 = 14'b00000010001111;
parameter rx7 = 14'b00000001010000;
parameter rx8 = 14'b10000000110001;
always @(posedge OSC_CLK or negedge RESET)
if(!RESET)
begin
tsclk0_sampled <= 1'h0;
tsclk0_sampled2 <= 1'h0;
end
else
begin
tsclk0_sampled2 <= TSCLK0;
tsclk0_sampled <= tsclk0_sampled2;
end
//RX SPORT section
always @(negedge /*TSCLK0*/tsclk0_sampled2 or negedge RESET)
if(!RESET)
begin
state2 <= 14'h0;
end
else
begin
case(state2)
idle:
if(TFS0)
state2 <= rx_dly;
else
begin
state2 <= idle;
end
rx_dly: state2 <= rx1;
rx1: state2 <= rx2;
rx2: state2 <= rx3;
rx3: state2 <= rx4;
rx4: state2 <= rx5;
rx5: state2 <= rx6;
rx6: state2 <= rx7;
rx7: state2 <= rx8;
rx8: begin
if(TFS0)
state2 <= rx_dly;
else
state2 <= idle;
end
default: state2 <= idle;
endcase
end
//TX SPORT section
always @(posedge RSCLK0 or negedge RESET)
if(!RESET)
begin
state1 <= 14'h0;
DR0PRI <= 1'h0;
READY <= 1'h1;
end
else
begin
case(state1)
idle: begin
READY <= 1'h1;
if(START)
begin
state1 <= tx1;
end
else
begin
state1 <= idle;
DR0PRI <= 1'h0;
end
end
tx1: begin
READY <= 1'h0;
state1 <= tx2;
DR0PRI <= TR_DATA[7];
end
tx2: begin
state1 <= tx3;
DR0PRI <= TR_DATA[6];
end
tx3: begin
state1 <= tx4;
DR0PRI <= TR_DATA[5];
end
tx4: begin
state1 <= tx5;
DR0PRI <= TR_DATA[4];
end
tx5: begin
state1 <= tx6;
DR0PRI <= TR_DATA[3];
end
tx6: begin
state1 <= tx7;
DR0PRI <= TR_DATA[2];
end
tx7: begin
state1 <= tx8;
DR0PRI <= TR_DATA[1];
end
tx8: begin
DR0PRI <= TR_DATA[0];
/*if(START)
begin
state1 <= tx1;
end
else
begin
state1 <= idle;
end*/
state1 <= idle;
end
default: state1 <= idle;
endcase
end
assign RFS0 = state1[13];
assign NEW_REC = state2[13];
// RX
always @(posedge state2[12])
begin
REC_DATA[7] <= DT0PRI;
end
always @(posedge state2[11])
begin
REC_DATA[6] <= DT0PRI;
end
always @(posedge state2[10])
begin
REC_DATA[5] <= DT0PRI;
end
always @(posedge state2[9])
begin
REC_DATA[4] <= DT0PRI;
end
always @(posedge state2[8])
begin
REC_DATA[3] <= DT0PRI;
end
always @(posedge state2[7])
begin
REC_DATA[2] <= DT0PRI;
end
always @(posedge state2[6])
begin
REC_DATA[1] <= DT0PRI;
end
always @(posedge state2[5])
begin
REC_DATA[0] <= DT0PRI;
end
endmodule
A few questions:
1. What is the purpose of rx1,rx2,rx3,rx4,rx5,rx6,rx7,rx8,rx_dly,idle ? Why are they parameterized ?
2. As I see : "tsclk0_sampled2" is sampled using the "OSC_CLK" signal. However, it's also used in the second "always" under the "negedge" statement. this will yield a gated clock - correct ?