... directly flow through MN’s parasitical NPN transistor to VSS
This parasitic NPN transistor (in parallel to MN & DN) has its base quite well shorted to its emitter, hence its VCES will be much higher than the sum of VDP and Vpowerclamp.
... I found the ESD MOS drawed in finger-style,and the minimum distance between pickup and drain is 1.624um.so is the parasitic resister in series with DN(or DP) a problem to discharge the ESD current?
The shorted-base NMOS / pBJT clamp sees its Rb
overdriven by D-B (C-B) soft breakdown injection
and then the BJT turns on and carries most of the
ESD current.
The parasitic resistors in series with source and drain in output transistors usually are salicide-blocked, i.e. relatively high-resistive, by this limiting an ESD current, but of course thus also limiting the tolerable ESD event energy.
salicide = self aligned silicidethe silicide block (salicide is something else)
Sure, just a (typ.) factor of 20 ratio, s. the foll. data from a 0.18µm process: View attachment sheet_resistances.pdfadditional resistance is usually negligible
exactly that name qualifies a process step (aligning implant and silicide during s/d implantation) it is not the name of the material depositedsalicide = self aligned silicide
Sure, just a (typ.) factor of 20 ratio, s. the foll. data from a 0.18µm process: View attachment 57055
It matters a whole lot when the rest of the current loop
consists of less, perhaps negative differential, resistance.
Specifically what matters is the local resistance, close-in
to any defect that might lower breakdown voltage. The
mesh will reduce current crowding into that weak spot,
and it will do so more effectively at higher ohms/sq.
You want the net resistance to be low, but you want the
point resistance / spreading resistance to be high. Or the
ESD device to be perfect. Times half a billion served. Feel
lucky?
pBJT = parasitic BJT
For effective ESD protection the non-salicided S/D lengths must be a lot longer than for core transistors, s. here for a 0.18µm process:... sure and when the resistor is 0.01-square long how much does that matter?
What do you think is the (physical) difference between "resistance" and "the way current density distributes in it"?the additional absolute resistance provided by the unsilicided portion of the S/D seems is negligible, what matters is the way current density distributes in it
For effective ESD protection the non-salicided S/D lengths must be a lot longer than for core transistors, s. here for a 0.18µm process:
Hence the series resistors are much more in the order of 0.1 squares, or perhaps 10Ω instead of (salicided) .5Ω in the example above.
What do you think is the (physical) difference between "resistance" and "the way current density distributes in it"?
Hi dgnani,TSMC seems a bit more conservative ...
As of you second point, there is quite a bit of difference between absolute resistance and how the current density distributes across its section:
- silicided diffusion: most current is in the thin silicide layer (on top of diffusion), which will experience a very high avg current density and even higher peak currents because of current crowding
- unsilicided diffusion: the same current generates a much smaller peak current density because of its larger, homegeneous section
The parallel sum of pointwise resistances is the bulk.
I guess you are thinking of the resistance experiencing a given stressing voltages when we are considering that same resistance experiencing a given ESD current...
do you know which point of view is correct?
Sure, dgnani! Never meant to upset you, just put a bundle of questions.Erikl consider taking it down a notch, will ya?
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