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help me about ESD protection system

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longqingshan

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I have a doubt about ESD protection system showed in FIG.

There are two ESD current flow paths in PS and ND mode.
For instance, for PS mode, the ESD current can flow through DP to VDD, and then through power clamp to VSS. The ESD current can also directly flow through MN’s parasitical NPN transistor to VSS;
What I want to make sure is which path will triggered in reality?
And how to layout the ESD MOS, guard ring?
 

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leo_o2

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Lower resistance path will be triggerred first for practical layout.
 

erikl

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... directly flow through MN’s parasitical NPN transistor to VSS
This parasitic NPN transistor (in parallel to MN & DN) has its base quite well shorted to its emitter, hence its VCES will be much higher than the sum of VDP and Vpowerclamp.
 

longqingshan

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This parasitic NPN transistor (in parallel to MN & DN) has its base quite well shorted to its emitter, hence its VCES will be much higher than the sum of VDP and Vpowerclamp.
thanks for reply!
I viewed some IO pads in the TSMC standard IO libaray, I found the ESD MOS drawed in finger-style,and the minimum distance between pickup and drain is 1.624um.so is the parasitic resister in series with DN(or DP) a problem to discharge the ESD current?
 

leo_o2

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This parasite resistance is acceptable for ESD. So no problem with it.
 

erikl

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... I found the ESD MOS drawed in finger-style,and the minimum distance between pickup and drain is 1.624um.so is the parasitic resister in series with DN(or DP) a problem to discharge the ESD current?
The parasitic resistors in series with source and drain in output transistors usually are salicide-blocked, i.e. relatively high-resistive, by this limiting an ESD current, but of course thus also limiting the tolerable ESD event energy.
 

dick_freebird

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The purpose of blocking silicide is to produce a ballast
resistor which suppresses hot-spotting and current
hogging. Especially important when a (parasitic) BJT
is doing most of the work. MOS and forward diodes
share / spread current well, naturally; reverse diode
breakdown and BJTs (both of which play in many ESD
schemes, especially NMOS breakdown clamps) do not.
You accept some inferior conduction performance as
the price of raw self-survivability.

The shorted-base NMOS / pBJT clamp sees its Rb
overdriven by D-B (C-B) soft breakdown injection
and then the BJT turns on and carries most of the
ESD current. This all happens at currents above
what you can push with a parameter analyzer and
what could be withstood at long duration, and is
often left unmodeled in PDKs.
 
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erikl

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The shorted-base NMOS / pBJT clamp sees its Rb
overdriven by D-B (C-B) soft breakdown injection
and then the BJT turns on and carries most of the
ESD current.
Isn't it an nBJT (lateral NPN, collector = Nwell) ?
 

dgnani

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The parasitic resistors in series with source and drain in output transistors usually are salicide-blocked, i.e. relatively high-resistive, by this limiting an ESD current, but of course thus also limiting the tolerable ESD event energy.
the silicide block (salicide is something else) additional resistance is usually negligible, the effect though is to redistribute the ESD current over the whole diffusion section and avoid the current crowding effects due to the inhomogeneity of the silicide layer
 

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dgnani

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salicide = self aligned silicide
exactly that name qualifies a process step (aligning implant and silicide during s/d implantation) it is not the name of the material deposited
Sure, just a (typ.) factor of 20 ratio, s. the foll. data from a 0.18µm process: View attachment 57055
sure and when the resistor is 0.01-square long how much does that matter?
 

dick_freebird

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It matters a whole lot when the rest of the current loop
consists of less, perhaps negative differential, resistance.

Specifically what matters is the local resistance, close-in
to any defect that might lower breakdown voltage. The
mesh will reduce current crowding into that weak spot,
and it will do so more effectively at higher ohms/sq.

You want the net resistance to be low, but you want the
point resistance / spreading resistance to be high. Or the
ESD device to be perfect. Times half a billion served. Feel
lucky?

pBJT = parasitic BJT
 
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dgnani

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It matters a whole lot when the rest of the current loop
consists of less, perhaps negative differential, resistance.

Specifically what matters is the local resistance, close-in
to any defect that might lower breakdown voltage. The
mesh will reduce current crowding into that weak spot,
and it will do so more effectively at higher ohms/sq.

You want the net resistance to be low, but you want the
point resistance / spreading resistance to be high. Or the
ESD device to be perfect. Times half a billion served. Feel
lucky?

pBJT = parasitic BJT
Not sure if you are agreeing with my statement or not, you are countering my statement but do not seem to state anything different:
the additional absolute resistance provided by the unsilicided portion of the S/D seems is negligible, what matters is the way current density distributes in it

Not sure what the half a billion served part is about either...
 

erikl

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... sure and when the resistor is 0.01-square long how much does that matter?
For effective ESD protection the non-salicided S/D lengths must be a lot longer than for core transistors, s. here for a 0.18µm process:

Hence the series resistors are much more in the order of 0.1 squares, or perhaps 10Ω instead of (salicided) .5Ω in the example above.

the additional absolute resistance provided by the unsilicided portion of the S/D seems is negligible, what matters is the way current density distributes in it
What do you think is the (physical) difference between "resistance" and "the way current density distributes in it"?
 

dick_freebird

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The distinction lies in bulk vs pointwise resistance. The parallel
sum of pointwise resistances is the bulk.

In the past I'be found it useful to model the ESD clamp as a
stack of unit-contact slices, looking at the effect of having
one "slice" have a (say) 1V-depressed breakdown under ESD
conditions. If the contact current exceeds pulse-regime rules
then you have some more thinking to do.

The last time I looked at this was during a challenge to ESD
layout rules, where we had a crazy long legacy pullback
length, and wanted to determine what was really needed.
We moved to half the extent without impact to self-
ruggedness int he clamp, and gained significant layout
compactness.

In large devices fully laid out, I see pullback resistance
coming in at about 20-25% of the net on resistance
of power switch paths. Pad exposed drains ought to
be laid out the same as protection devices, or they
become the weak link.
 
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dgnani

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For effective ESD protection the non-salicided S/D lengths must be a lot longer than for core transistors, s. here for a 0.18µm process:

Hence the series resistors are much more in the order of 0.1 squares, or perhaps 10Ω instead of (salicided) .5Ω in the example above.


What do you think is the (physical) difference between "resistance" and "the way current density distributes in it"?
TSMC seems a bit more conservative than IBM when it comes to this but I did some digging in one of IBM ESD manuals (I highly recommend them if you have the opportunity) and found (besides what I and -I think- dickfreebird mentioned about current redistribution) that the absolute value of the (clumped) resistor does actually change the sustain voltage during snapback so you are right this small resistance matters during the ESD discharge

As of you second point, there is quite a bit of difference between absolute resistance and how the current density distributes across its section:
- silicided diffusion: most current is in the thin silicide layer (on top of diffusion), which will experience a very high avg current density and even higher peak currents because of current crowding
- unsilicided diffusion: the same current generates a much smaller peak current density because of its larger, homegeneous section

dickfreebird thank you for your explanations
 
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erikl

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TSMC seems a bit more conservative ...
Hi dgnani,
this doesn't originate from TSMC ...

As of you second point, there is quite a bit of difference between absolute resistance and how the current density distributes across its section:
- silicided diffusion: most current is in the thin silicide layer (on top of diffusion), which will experience a very high avg current density and even higher peak currents because of current crowding
- unsilicided diffusion: the same current generates a much smaller peak current density because of its larger, homegeneous section
I'd think -- with a factor of 20 higher sheet resistance -- there won't flow the same current.

The parallel sum of pointwise resistances is the bulk.
So the bulk resistance is the integral over all pointwise resistances, isn't it? Intrinsically tied to each other, inseparably. How then can the former one be negligible and the latter ones do matter?

Do you think of an effect of inhomogeneously distributed ("pointwise") scattering (resistance) centers rendering the partial currents more uniform than from a homogeneous distribution?

May be we dispute about nothing! ;-)
No harm meant!
erikl
 

dgnani

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Erikl consider taking it down a notch, will ya?

I guess you are thinking of the resistance experiencing a given stressing voltages when we are considering that same resistance experiencing a given ESD current...
do you know which point of view is correct?
 

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Human body model can be considered constant current.
It has plenty of backing voltage and a high value resistor.

Machine model is more like constant voltage, only a small
inductance.

The more useful (not to say correct) way of looking at it
varies by the threat model.

I prefer to think in terms of the current loop, minimizing the
voltage imposed to return the current to its source. But I
also have seldom been given a hard and fast MM or CDM
tasking, while HBM receives a lot of interest specwise. I
tend to work on products that are still human-handled.

You can think of the ballasting as the same thing done in
old bipolar power amplifiers - if you parallel transistors,
you will add emitter ballast (degeneration) resistors to
prevent runaway of the weakest.

While the device is notionally uniform, there is always an
amount of defectivity and a local variation in I=V curve
(if you could decompose the gross current as easily on
the bench, as in analysis; more often a burnt spot is likely
to be your only available indication).

So there will always be a weakest point. Ballast resistance
throttles how badly the wimp can be taken advantage of.
 
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erikl

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I guess you are thinking of the resistance experiencing a given stressing voltages when we are considering that same resistance experiencing a given ESD current...
do you know which point of view is correct?
Now I think both points of view play a role:
  • the larger series resistance will reduce the peak current, so protecting the ESD protecting device itself - but by this limiting the ESD generated voltage to a higher value, as mentioned in my former contribution above
  • the larger series resistance will undoubtedly make sure and harmonize the current densities along the finger widths, as dick_freebird pointed out with his comparison with emitter ballast (degeneration) resistors

Erikl consider taking it down a notch, will ya?
Sure, dgnani! Never meant to upset you, just put a bundle of questions.
I'll give in now, not without stating you are right! And -- as we say here in Bavaria: "Who is right, [he] pays for a Mass" (1 liter of beer) ;-)
 

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