Help in Verilog Code

[ramdin2006]

I am writing program to add two sparse matrix to work in vivado 2016.2 and I am not able to get the output properly. If anyone is interested in helping me out, it will be a great help for me.

Following is the verilog code which i tried out/
This program should add two sparse matrix by finding the non-zero terms and give output matrix.

---

Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
//
module matrix();
 reg sp1[9:0][0:2];
 reg sp2[9:0][0:2];
 reg sp3[9:0][0:2];
 integer r,c,i,j,k,t,tot_val,k1,k2,k3,tot1,tot2;
begin
            
       k=1;
    for(i=0;i < r;i=i+1)
       begin
               for(j=0;j<c;j=j+1)
         begin
                  if( t != 0 )
             begin           
                                sp[k][0] = i;
                                sp[k][1] = j;
                                sp[k][2] = t;
                                k=k+1;
     
             end
             end
             
        sp[0][0] = r;
        sp[0][1] = c;
        sp[0][2] = k-1;
     
 
 begin      
       r = sp[0][0];
       c = sp[0][1];
       tot_val = sp[0][2];
for(i=0;i<r;i=i+1)
       begin
 for(j=0;j<c;j=j+1)
 begin
 for(k=1;k<=tot_val;k=k+1)
 begin
 if(sp[k][0]==i && sp[k][1]==j)
 break;
 end
 if(k>tot_val)
 $display ("0");
 else
 $display ("%4d",sp[k][2]);
 end
 end
 end     
    
 begin
 if(sp1[0][0] != sp2[0][0] || sp1[0][1] != sp2[0][1])
 begin
 $display("Invalid Matrix Size");
 exit(0);
 end   
    tot1 = sp1[0][2];
       tot2 = sp2[0][2];    
      k1 = 1;
      k2 = 1;
      k3 = 1;
     
while ( k1 <= tot1 && k2 <= tot2)
      
              if ( sp1[k1][0] < sp2[k2][0] )
                   begin
                           sp3[k3][0] = sp1[k1][0];
                         sp3[k3][1] = sp1[k1][1];
                           sp3[k3][2] = sp1[k1][2];
                          k3=k3+1;
                          k1=k1+1;
           end
                 
                 else 
                 if ( sp1[k1][0] > sp2[k2][0] )
                   begin
                            sp3[k3][0] = sp2[k2][0];
                        sp3[k3][1] = sp2[k2][1];
                             sp3[k3][2] = sp2[k2][2];
                           k3=k3+1;
                          k2=k2+1;
                 end
                 
                 else if ( sp1[k1][0] == sp2[k2][0] )
                  
                  if ( sp1[k1][1] < sp2[k2][1] )
               begin
                        sp3[k3][0] = sp1[k1][0];
                           sp3[k3][1] = sp1[k1][1];
                          sp3[k3][2] = sp1[k1][2];
                       k3=k3+1;
                       k1=k1+1;
                    end 
                     else 
                     if ( sp1[k1][1] > sp2[k2][1] )
               begin
                       sp3[k3][0] = sp2[k2][0];
                          sp3[k3][1] = sp2[k2][1];
                          sp3[k3][2] = sp2[k2][2];
                       k3=k3+1;
                       k2=k2+1;
                    end
                     else 
                  
                          sp3[k3][0] = sp2[k2][0];
                        sp3[k3][1] = sp2[k2][1];
                         sp3[k3][2] = sp1[k1][2] + sp2[k2][2];
                         k3=k3+1;
                         k2=k2+1;
                         k1=k1+1;
           
         while ( k1 <=tot1 )
                 sp3[k3][0] = sp1[k1][0];
                     sp3[k3][1] = sp1[k1][1];
                  sp3[k3][2] = sp1[k1][2];
               k3=k3+1;
               k1=k1+1;
       
       
        while ( k2 <= tot2 )
       
               sp3[k3][0] = sp2[k2][0];
                   sp3[k3][1] = sp2[k2][1];
                 sp3[k3][2] = sp2[k2][2];
               k3=k3+1;
               k2=k2+1;
            
         sp3[0][0] = sp1[0][0];
       sp3[0][1] = sp1[0][1];
       sp3[0][2] = k3-1;
          
 end
endmodule
 
//

---

 

[TrickyDicky]

What exactly is the problem? apart from the fact you're trying to write software with Verilog HDL...

 

[dpaul]

Typical software approach....
Rewrite the code without using for and while loops. Then come back here with the problem you face.

 

[FvM]

Following is the verilog code which i tried out

1. The code has syntax errors. How can you have it "tried out"? You'll first correct the syntax errors according to error messages.
2. It's not synthesizable in hardware (quite trivial, it has no in- and output ports. A bit more involved, it uses loops with variable bounds that can't be enrolled by a synthesis tools). If you fix the loops, the purely combinational design will unlikely fit a reasonable FPGA. If it does though, it's running very slow.

Did you intend to synthesize the design in FPGA, then restart the project as suggested. If it's only intended to be run in a simulator, it might work after correcting the syntax errors.

 

[ads-ee]

Interesting piece of software that isn't even correctly written Verilog software code.

 reg sp1[9:0][0:2];
 reg sp2[9:0][0:2];
 reg sp3[9:0][0:2];
 integer r,c,i,j,k,t,tot_val,k1,k2,k3,tot1,tot2;

        sp[0][0] = r;
        sp[0][1] = c;
        sp[0][2] = k-1;

How is this supposed to work, the signal sp doesn't even exist in the design so is going to default to a net type of wire and it's only going to be a single bit wide, so the array indexing is going to FAIL.

tot_val = sp[0][2];

Assuming this sp signal is declared the same as sp1, sp2, and sp3, then this is assigning a single bit value to the tot_val as you are indexing into a 2D array of 1-bit values.

Along with all these poorly used Verilog features you are also using the big no-no of integers as part of your code, that aren't meant for indexing but holding data. The Verilog integer type is inherently 32-bits and can and will cause problems if not handled properly.

The whole code is filled with these types of misconceptions of Verilog. My advice stick with C programming, or if you are required to produce a hardware implementation then draw a schematic of a digital design that performs this matrix operation and then describe that design in Verilog at a hardware level. You may want to learn the Verilog language first before attempting this or at least learn the synthesizable constructs that produce the various digital circuits, e.g. FFs, multiplexers, demultiplexers, gates, etc.

Based on what you've posted I am sure the Verilog instruction at your school is at best inadequate (more likely non-existent). Probably boils down to "Ask Verilog questions on edaboard" and "Look at websites on Verilog to learn the language" (FYI, almost all of the tutorial websites on Verilog are rubbish).

 

[ramdin2006]

I was trying to recreate the program from c to verilog ! Since I am familiar with C language, I started writing in C at first. But now I need to implement this in a hardware so I was trying to write in verilog for fpga implementation. Any suggestions for converting C to verilog ?

 

[ads-ee]

I was trying to recreate the program from c to verilog ! Since I am familiar with C language, I started writing in C at first. But now I need to implement this in a hardware so I was trying to write in verilog for fpga implementation. Any suggestions for converting C to verilog ?

Look at the C code figure out the algorithm, then develop an FSM that performs the algorithm (using a clock) by read the matrix values from RAMs and writing them to another RAM. If you lack any hardware background you are going to run into a lot of issues with using Verilog based on a knowledge of C.

Verilog is not C and can not be used like C. Some of the language syntax is the same but that is it. The way it "executes" and is synthesized is totally different.