AbinayaSivam
Member level 1
Hi,
No Compilation error but logic of timing diagram is wrong.
I am generating Trigger signal for 500ns, and every neck edge (either positive or negative) of Trigger i am trying to store the counter in Register. Can anyone verify me code. I have simulated verilog Code in Quartus but in NIOS i am getting incorrect result.
Please verify my code whether it is right or wrong.
No Compilation error but logic of timing diagram is wrong.
I am generating Trigger signal for 500ns, and every neck edge (either positive or negative) of Trigger i am trying to store the counter in Register. Can anyone verify me code. I have simulated verilog Code in Quartus but in NIOS i am getting incorrect result.
Code:
module Counter(
input clk, // Clk 50Mhz
input enable,
input reset,
output reg[31:0] Final_value
// output wire trig
);
reg[31:0] counter_out;
reg [7:0] temp=0;
reg [31:0] counter_result;
wire temp1;
wire temp2;
reg trig;
always@(posedge clk or negedge reset)
begin
if(~reset)
begin
trig<=0;
temp<=0;
counter_out<=0;
end
else if (enable==1'b1) // Condition
begin
counter_out<=counter_out+1; // Making delay
temp<=temp+1;
if(temp==25)
begin
temp<=0;
trig<=~trig; // Generating Trigger Signal for 500ns
end
end
end
assign temp1=trig;
assign temp2=temp1&&clk;
always@(posedge temp2 or negedge reset)
if(~reset)
counter_result<=0;
else
begin
counter_result<=counter_result+1; // Generating Counter Data
end
always@(posedge trig or negedge reset)
if(~reset)
Final_value<=0;
else
begin
Final_value<=counter_result; // Collecting Edge value of Trigger signal into Regsiter [Final_value]
end
endmodule
Please verify my code whether it is right or wrong.