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help in verilog code for an 8*8 mutiplier

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deepavlsi

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help in verilog code

hello everbody

i need help from verilog, if anybody having the smulated result both input and output for an 8*8 mutiplier using verilog , can u send it to me?

thanks,
deepa.v
 

Syswip

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Re: help in verilog code

Hi deepavlsi,

Could you please be a little bit more detailed.

Do you want the following module?

Code:
module mult8x8 (in1, in2, out);

input [7:0] in1, in2;
output [15:0] out;

assign out = in1 * in2;

endmodule

Bests,
Syswip
https://syswip.com/
 

deepavlsi

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Re: help in verilog code

hi

thanks for ur reply, actually this is the help i'm expecting from ur people .. i have downloaded the pipelined 8*8 multiplier code from net, but while i simultaing that ,im not able to get simultaed result, and also i didnt know how to force the input..so if u have any idea ,how to force the input for an 8*8 pipelined multiplier kindly explain to me...


thanks
deepa.v
Syswip said:
Hi deepavlsi,

Could you please be a little bit more detailed.

Do you want the following module?

Code:
module mult8x8 (in1, in2, out);

input [7:0] in1, in2;
output [15:0] out;

assign out = in1 * in2;

endmodule

Bests,
Syswip
https://syswip.com/
 

deepavlsi

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hi thanks for ur reply


actually i have doubt regarding simulated result...i have written the code for an 8*8 pipelined multiplier..afterthat i have done a compilation successfully, but now i want to check out the simulated output for an this multiplier..to view the simulated waveform , i didnt know how to force input ...


thanks...
 

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