Help in FPGA Design(Xilinx LUT-4 Problem)

[sekonder85]

xilinx lut4

Hi everyone,
I am working on a project that uses spartan series FPGA. In my design includes 4 top-block and they include sub blocks and goes like that. The problem is that when I tries to synthesize the whole project I see that my LUT-4 is used %95 but it is not possible. Because my FPGA is enough big for my project. But when I synthesize the my 4 block I see that LUT-4 usage does not exceed %2 for each. I ask that what causes this increased LUT-4 usage when I synthesize whole design which combines only these 4 blocks ...

Thanks for helps...

 

[tlp71@hotmail.com]

lut-4

may be that when you sintetyze your blocks alone, xst cut a lot of logic unconnect.
when you try whit the entire project you can't remove anithing.
the best way to check what happens is to open a case whit xilinx.
you can send him your project and they can reply.
or if you like you can share your project whit others.
bye.
g.

 

[sekonder85]

lut vs lut4 in fpga

Thanks for reply but I found the reason and solve it...

 

[cherukukeshav]

lut design

Can u share it with us, so that it can help others. what was the problem and solution...

- Keshav