Help in FPGA and Verilog

[reyge]

What are the verilog coding considerations when getting signals outside of an FPGA board?

I am implementing a code that gets an input signal either inside or outside of the FPGA (actually coming also from another FPGA board). So the user can choose whether to have an internal or external input. However, when the external input is chosen, the output becomes different... I assume that the external connection is ok... I have put buffers on the input and i think i have a fully synchronous design.. what else could i possibly be missing?

thanks a lot!

 

[avimit]

Hi,
I wonder what frequency you are working on. Is the path from external world meeting your timing requirements? The chances are the external siganal may consume a lot of time to reach your design, and may not be used in the clock cycle you are assuming it would be used.
you 'think' that your design is sync. But what if it is not sync. The chances are you will get unexpected results, if the external siganl is out of sync with your clock.
Kr,
Avi
http://www.vlsiip.com

 

[reyge]

the path from external world is an ide cable around 6 inches only and my master clock is 50MHz.. i assume the ide cable can handle this frequency without any errors right?