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Hi,
I have a design in mixed language (VHDL,Verilog)!
I want to deliver it to my customer to be used in Vivado.
1) How can I encrypt or obfuscate it to be used as a black box in vivado?
I made .dcp or .edf files that can be added to vivado, but these are netlists and can be read by anyone! by opening the dcp file I can find my design in schematics.
2) is there any method to remove design hierarchy?(may be this one helpful for me!)
I visited the page below about encrypting.
3) is the Synopsys's VMC encrypted design, synthesizeable by Viavdo?
https://www.edaboard.com/showthread.php?t=98878
I have a design in mixed language (VHDL,Verilog)!
I want to deliver it to my customer to be used in Vivado.
1) How can I encrypt or obfuscate it to be used as a black box in vivado?
I made .dcp or .edf files that can be added to vivado, but these are netlists and can be read by anyone! by opening the dcp file I can find my design in schematics.
2) is there any method to remove design hierarchy?(may be this one helpful for me!)
I visited the page below about encrypting.
3) is the Synopsys's VMC encrypted design, synthesizeable by Viavdo?
https://www.edaboard.com/showthread.php?t=98878