Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

help in encrypting Verilog code

Status
Not open for further replies.

haneet

Full Member level 3
Joined
Nov 7, 2006
Messages
160
Helped
14
Reputation
28
Reaction score
1
Trophy points
1,298
Activity points
2,219
hello frndz,
i hav a verilog code which i want to encrypt using Modelsim so that the final file is in the format such as "1010.." so that the user doesnt know wht the code is but is successful in using the file in his application.

thanks in advance
 

VLOG -NODEBUG , PLS TRY THIS.
 

use AES in Modelsim
 

@funzero,
this command of "vlog ---.v -nodebug" doesnt work. it shows cannot open file ---.v
could u plz suggest some other alternative...
 

FLEXcertifydll said:
Same with the topic

There are several options with varying levels of protection:

1. Use `protect/`endprotect, then tools like Modelsim/VCS/NC can encrypt them.
2. Ship compiled library such as "work" in Modelsim. The downside is end user is restricted to same tool chain and may be even versions.

3. Use special IP encryption that comes with your tool such as "-nodebug" with Modelsim (Look in their doc for more), gen_ip in VCS etc.

4. Use specialized tool such as Synopsys's VMC. My team has lot of experience in this especially with SystemVerilog.


HTH
Ajeetha, CVC
www.noveldv.com
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top