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[SOLVED] help in correcting errors in fifo verilog code

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theHermes

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HI, this is my code for synchronous fifo.I have tried to correct errors as much as possible but I have not suceeded. The error it says is illegal left hand assignment and shows many places.but I don`t know how to correct? Thanks for ur help.

`timescale 1ns / 1ps
module fifo2 (wr, rst,clk,rd,din,full, empty,dout);

input wr,rd,clk,rst;
input [7:0] din;
output full,empty;
output [7:0] dout;
integer count,tmp;
reg [7:0]memory[15:0];
initial
begin
count=0;
tmp=0;
end


always@ (posedge clk)
begin

if (rst == 1)
begin
dout <= 0;
empty <= 0;
full <= 0;
end

if (wr == 1)
begin
if(count == 15)
begin
full <= 1;
end
else
begin
full <= 0;
empty <= 0;
memory[count] <= din;
count <= count + 1;
end
end

else if (rd == 1)
begin
if(count == 0)
begin
dout <= 0;
empty <= 1;
end
else if (count == 1)
begin
empty <= 0;
full <= 0;
dout <= memory[0];
count <= count - 1;
end
else
begin
empty <= 0;
full <= 0;
dout <= memory[0];
for (tmp = 0; tmp<15 ; tmp = tmp + 1)
memory[tmp] <= memory[tmp + 1];
count <= count - 1;
end

end
end
endmodule
 

j_andr

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if you assign a value inside 'always' block
the object has to be declared as 'reg';

add 'reg' to the declaration:
output reg full,empty;
the same for dout;

J.A
 

theHermes

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the code now has no errors. thanks a lot!!
 

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