Help for testBench of MODELSIM

[Adnan86]

When I write test bench for may VHDL project , when I use
clk <= not clk after 5 ns ;
this be continue forever but if I want to stop it for example after 2000 ns , what can i do for solve it .
I'll be preciate if someone help .
thanks

 

[syedshan]

you can use following inside process

signal  t1 : time;
...
...
if(t1 >= 1000 ns) then
 assert false report "Simulation stop at time " severity failure;
end if;

This will stop simulation and assert failure notice, which is output by you deliberately

 

[Adnan86]

thanks , i did it but didnt work .

 

[TrickyDicky]

you can use following inside process

signal  t1 : time;
...
...
if(t1 >= 1000 ns) then
 assert false report "Simulation stop at time " severity failure;
end if;

This will stop simulation and assert failure notice, which is output by you deliberately

That wont work until you're constantly updating the t1 signal with the current time.

Something like this might be more appropriate:

---

Code VHDL - [expand]
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process
begin
  wait for 200 ns;
 
  assert false report "Time to end the simulation" severity failure;
 
end process;

---

but using a failed a assert is the bluntest way to kill the simulation. The most elegant is to kill all stimulus:

---

Code VHDL - [expand]
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ENDSIM <= false, true after TIMEOUT_PERIOD;
 
process
begin
  if clk /= '1' then
    clk <= '1';
  else
    clk <= '0';
  end if;
  
  wait for CLK_PERIOD/2;
 
  if ENDSIM then 
    report "Clock suspended" severity NOTE;
    wait;
  end if;
end process;
 
 
--stimulus process
process
begin
  wait until rising_edge(clk)
 
  --do some stimulus generation
 
  if ENDSIM then
    report "Stimulus Stopped" severity NOTE;
    wait;
  end if;
end process;

---

- - - Updated - - -

The second process may finish while waiting for a clk, so you can modify it to do:

wait until rising_edge(clk) or ENDSIM;

 

[Adnan86]

thanks it worked ..

 

[rajavel.rv]

Hi, How i can use ENDSIM in vhdl test bench code... ENDSIM <= false, true after 1000 ns;
am use this syntax in my vhdl code but it showing the error :

1. Illegal target for signal assignment.
2. (vcom-1136) Unknown identifier "endsim".
3. Enumeration literal "true" is type std.standard.boolean; expecting type (error).

If anyone library file have to execute for this syntax...

 

[TrickyDicky]

ENDSIM is nothing special, you just need to declare it as a signal of type boolean in your testbench.
ENDSIM will NOT stop a testbench automatically, only if you design your testbench to stop the simulation when ENDSIM is true.

 

[dave_59]

In VHDL 2008 you can just call stop() or finish() to exit the simulation.

https://www.doulos.com/knowhow/vhdl_designers_guide/vhdl_2008/vhdl_200x_small/