PigiPigi,
firstly, you can try to do functional verification, i.e. run simulation without .sdf file. if everything ok, then proceed to next.
2. run timing verification, i.e. run simulation with .sdf. if everything ok, then your design is 99% working. if not proceed to next.
3. you can try to reduce your system clock by half, and run simulation. if it's ok now. proceed to next. if not ok, reduce system clock by another half.
4. recoding and resynthesize by tighten the constraint of your design. or probably reduce your system clock requirement if possible.
Hope it helps
always@smart