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help for ius6.2 simulation?

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aprice

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timescale of worklib module = notset

help for ius6.2 simulation?

when i simulate my verilog design using the following command:
ncverilog hello.v

some ERRORs occur:

ncverilog(64): 06.20-s005: (c) Copyright 1995-2008 Cadence Design Systems, Inc.
file: hello.v
module worklib.hello:v
errors: 0, warnings: 0
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Building instance overlay tables: .................... Done
Generating native compiled code:
worklib.hello:v <0x3eff1d51>
streams: 1, words: 476
Loading native compiled code: .................... Done
Building instance specific data structures.
Design hierarchy summary:
Instances Unique
Modules: 1 1
Initial blocks: 1 1
Simulation timescale: 100ps
Writing initial simulation snapshot: worklib.hello:v
ERROR: can't determine installation root.
can't create rooted path to arg0 "ncroot"
using current working directory or $PATH


when i use "irun hello.v",it has the same errors.

i have set the environment variable CDS_ROOT to ius62 installation directory
 

it is solved by myself, the reason is that i do not set path
 

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