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Help for BIST controller

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fabienbibi

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Hello everybody,

I'm at the moment doing a job placement at the university of Stuttgart and I have to program a BIST controller in VHDL to control other modules such as the LFSR, the DUT, phase shifters and the MISR.

I want the BIST controller to be a finite state machine. I have severals states like : initial_s, LFSR_dut_s, testing_s, MISR_dut_s and MISR_s.
During my state initial_s, I set the counter to 0. When start is equal to 1, my state is set to the LFSR_dut_s. During that state if my counter is equal to 'd' then my state changes to testing_s and my counter is set to 0. And it is the same for the other states.

The problem is that my counter is never set to zero after 'd' cycles in the LFSR_DUT_s state and I don't know why. I have been looking into the matter for a while but I have not found a solution. Can someone please help me?

Here is my code written bellow:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

entity bist_ctrl3 is

-- d is the number of shiftings to be done which equals the width of the shift register (DUT)
-- addr_depth is the number of bits required to obtain the depth of the memories
-- no-patterns_compacted is the number of patterns to be compacted by the MISR

generic ( d : integer := 3; addr_depth : integer := 8; no_patterns_compacted : integer := 1 );

port (
clk,reset_n,start: in std_logic;
data_in_en_misr : out std_logic; -- data in MISR enable
seed_lfsr_en : out std_logic; -- Seeding LFSR enable
cycles : in natural; -- Number of cycles
comparator_en : out std_logic; -- Compare enable
dut_se: out std_logic; -- data shifting enable for the DUT
comparator_sig : in std_logic; -- Signal from the comparator
write_fail_mem : out std_logic; -- Write fail memory enable signal
write_response_mem : out std_logic; -- Write response memory enable
write_seed_mem : out std_logic; -- Write seed memory enable
lfsr_se : out std_logic; -- LFSR shifting enable signal
misr_se : out std_logic; -- MISR compacting enable signal
pattern_index_out: out natural; -- Pattern number indication
addr_fail_out: out std_logic_vector(addr_depth-1 downto 0);
addr_response_out : out std_logic_vector(addr_depth-1 downto 0);
addr_seed_out : out std_logic_vector(addr_depth-1 downto 0);
addr_seed_out_write : out std_logic_vector(addr_depth-1 downto 0);
addr_response_out_write : out std_logic_vector(addr_depth-1 downto 0));

end entity;

architecture bhv of bist_ctrl3 is

type etat is (initial_s,lfsr_dut_s, misr_dut_s, misr_s, testing_s);
signal state, state_next : etat;
signal counter, counter_next: std_logic_vector(8 downto 0);
signal addr_int_sig_fail: std_logic_vector(addr_depth-1 downto 0);
signal addr_int_sig_response : std_logic_vector(addr_depth-1 downto 0);
signal addr_int_sig_seed : std_logic_vector(addr_depth-1 downto 0);
signal addr_int_seed_write: std_logic_vector(addr_depth-1 downto 0);
signal addr_int_response_write : std_logic_vector(addr_depth-1 downto 0);



begin
--------------------------------------------------------------------------------------------------------
-- Final State Machine for BIST Controller management
--------------------------------------------------------------------------------------------------------
process(clk,reset_n)

begin
if reset_n='0' then
data_in_en_misr <='0';
state <= initial_s;
counter <= (others => '0'); -- initialisation of counter

elsif clk'event and clk='1' then
state<=state_next;
counter<=counter_next;

end if;

end process;

process(state,start,counter, state_next, counter_next)

begin
state_next <= state;
counter_next <= counter;

case state is
when initial_s => counter_next <= (others => '0');
if start = '1' then
state_next <=lfsr_dut_s;
counter_next <= (others => '0');
end if;

when lfsr_dut_s => if counter = d then
state_next <= testing_s;
counter_next <= (others => '0');
end if;


when testing_s => if counter = 1 then
state_next <= misr_dut_s;
counter_next <= (others => '0');
end if;


when misr_dut_s => if counter = 1 then
data_in_en_misr <='1';
else data_in_en_misr <= '0';
end if;
if counter = (d*no_patterns_compacted) then
state_next <= misr_s;
counter_next <= (others => '0');
end if;

when misr_s => if counter = 1 then
state_next <= testing_s;
counter_next <= (others => '0');
end if;


end case;
counter_next<=std_logic_vector(unsigned(counter))+1;


end process;

lfsr_se <= '1' when (state = lfsr_dut_s or state = misr_dut_s) else '0';
dut_se <= '1' when (state = lfsr_dut_s or state = misr_dut_s) else '0';
misr_se <= '1' when (state = misr_dut_s or state = misr_s) else '0';

end bhv;



thank you.

Fabien
 

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