Library IEEE;
Use IEEE.std_logic_1164.all;
Entity lab4bTB is
end;
Architecture comparator of lab4bTB is
signal altb_i, agtb_i: std_logic:='0';
signal aeqb_i: std_logic:='1';
signal a,b: std_logic_vector(3 downto 0):="0000";
signal agtb_o,agtb_out, aeqb_o,aeqb_out, altb_o, altb_out : std_logic;
begin
UUT : entity work.lab4b port map(altb_i, agtb_i, aeqb_i, a, b, altb_out, agtb_out, aeqb_out);
tb : process
begin
wait for 50 ns;
aeqb_i <= '1'; a<="1110";
wait for 50 ns;
aeqb_i <= '1'; b<="1111";
wait for 50 ns;
aeqb_i<='0'; agtb_i <='1';
wait for 50 ns;
a<="1010"; b<="1111";
wait for 50 ns;
agtb_i <='0'; altb_i<='1';
wait for 50 ns;
a<="1111"; b<="1010";
end process tb;
aeqb_o<=aeqb_out;
agtb_o<=agtb_out;
altb_o<=altb_out;
end;