[help!] Error while compiling in modelsim

[jianhuachews]

Hi guys.. I was writing a testbench but errors occurred when i compiled it. could anyone tell me wht's wrong? I know it might look pretty obvious but i just don't see it.

The errors while compiling the test bench goes
Signal "altb_i" is type std_logic; expecting type std_logic_vector.
Signal "agtb_i" is type std_logic; expecting type std_logic_vector.
Signal "a" is type std_logic_vector; expecting type std_logic.
Signal "b" is type std_logic_vector; expecting type std_logic.


TB code

Library IEEE;
Use IEEE.std_logic_1164.all;

Entity lab4bTB is
end;

Architecture comparator of lab4bTB is
	signal altb_i, agtb_i: std_logic:='0';
	signal aeqb_i: std_logic:='1';
	signal a,b: std_logic_vector(3 downto 0):="0000";
	signal agtb_o,agtb_out, aeqb_o,aeqb_out, altb_o, altb_out :  std_logic;

begin
UUT : entity work.lab4b port map(altb_i, agtb_i, aeqb_i, a, b, altb_out, agtb_out, aeqb_out);


tb : process
	begin
		wait for 50 ns;
		aeqb_i <= '1'; a<="1110"; 
		wait for 50 ns;
		aeqb_i <= '1'; b<="1111";
		wait for 50 ns;
		aeqb_i<='0'; agtb_i <='1';
		wait for 50 ns;
		a<="1010"; b<="1111";
		wait for 50 ns;
		agtb_i <='0'; altb_i<='1';
		wait for 50 ns;
		a<="1111"; b<="1010";
		
	end process tb;
	
	aeqb_o<=aeqb_out;
	agtb_o<=agtb_out;
	altb_o<=altb_out;
end;

program code

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity lab4b is port (
		a,b: in std_logic_vector(3 downto 0):="0000";
		altb_i: in std_logic:='0';
		aeqb_i: in std_logic:='1';
		agtb_i: in std_logic:='0';
		aeqb_o, agtb_o, altb_o: out std_logic
);

end;

architecture comparator of lab4b is

begin

	process (agtb_i, aeqb_i, altb_i, a, b)
	 begin
		if (aeqb_i='1') then
		 if (a=b) then
			aeqb_o <= '1';
			agtb_o <= '0';
			altb_o <= '0';
		 elsif (a>b) then
		 	agtb_o <='1';
			aeqb_o <='0';
			altb_o <='0';
		 elsif (a<b) then
		 	agtb_o <='0';
			aeqb_o <='0';
			altb_o <='1';
		elsif (agtb_i='1' or (altb_i='1' and a > b)) then
			agtb_o <='1';
			aeqb_o <='0';
			altb_o <='0';
		elsif (altb_i='1' or (agtb_i='1' and a < b)) then
			agtb_o <='0';
			aeqb_o <='0';
			altb_o <='1';
		else 
			aeqb_o<='0';
			agtb_o<='0';
			altb_o<='0';
		 end if;
		end if;
	end process;

end;

Thanks in adv!

 

[vipinlal]

The signals inside the entity instantiation was not in the correct order. Replace it with the below line:

UUT : entity work.lab4b port map(a,b,altb_i, aeqb_i, agtb_i,aeqb_out, agtb_out,altb_out);

 

[jianhuachews]

The signals inside the entity instantiation was not in the correct order. Replace it with the below line:

UUT : entity work.lab4b port map(a,b,altb_i, aeqb_i, agtb_i,aeqb_out, agtb_out,altb_out);

Hi vipinlal, thanks for helping out! I didn't know that the order actually affect the compilation.. It's actually working right now. Can you tell me more about it?

 

[sanju_]

hi
in your testbench line
UUT : entity work.lab4b port map(altb_i, agtb_i, aeqb_i, a, b, altb_out, agtb_out, aeqb_out);
it should be order with
entity lab4b is port (
a,b: in std_logic_vector(3 downto 0):="0000";
altb_i: in std_logic:='0';
aeqb_i: in std_logic:='1';
agtb_i: in std_logic:='0';
aeqb_o, agtb_o, altb_o: out std_logic
);

end;

 

[vipinlal]

Learn more about port mapping methods here:
VHDL coding tips and tricks: port mapping

 

[jianhuachews]

Thanks guys! I've gotten the waveforms i wanted but i was told that my vhdl code design is wrong and that it should be in hierarchy design. I don't get it. What's with hierarchy design coding and mine? And how should i go about implementing hierarchy design in my program?

 

[sanju_]

hi
he is asking you to do Component Structure model
look some examples
Design Hierarchy
LogicWorks - VHDL
VHDL coding tips and tricks: July 2010

 

[jianhuachews]

I have been reading for hours and i still don't get it..........