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HELP: Can't download *.pof file to my chip! (Altera CPLD)

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jtag pof

CPLD: Altera EPM3128ATC100-10
Software: MAX+plusII 10.2
Language: VHDL
License: full
OS: Windows 98/2000
Download type: Altera ByteBlaster MV
Download chip: 74HC244

In my project, I want download the *.pof file to my CPLD. But a warning message always jumps out: "Unrecognized device or socket is empty". I have checked my board, but there is nothing wrong. :(
In my board, I used 2 types power:3.3V for core, and 5V for IO port and there is no clock to drive the CPLD (This CPLD is designed as a substitute for a programmable buffered I/O expander, so there is no clock in it).

I think there must be somrthing wrong that I have not found, so please help me what possibility can make this error?

Thank you!
 

pof file special

Try on the shoter cable length between CPLD and 74hc244.
 

what is the meaning of pof files

Have you got the drivers installed and working for your byteblaster?
try connecting to the jtag port of you chip and pressing the autodected hardware button it should then find your chip. Make sure that you have checked the box that says program/configure besdie the .pof file entry in the programmer window. Make sure that your design is compiled for the exact chip that you are using. it should show the same chip when you load the file into the programmer and when you use the autodetect button in the programmer.
 

download cpld program from chip?

mc_navman said:
Have you got the drivers installed and working for your byteblaster?
try connecting to the jtag port of you chip and pressing the autodected hardware button it should then find your chip. Make sure that you have checked the box that says program/configure besdie the .pof file entry in the programmer window. Make sure that your design is compiled for the exact chip that you are using. it should show the same chip when you load the file into the programmer and when you use the autodetect button in the programmer.
Click to expand...

Thank you!
I have insalled the driver and confirmed. By the way I have shorted my cable(the length between 74HC244 and CPLD is 0.15m, the one between 74HC244 and PC is 0.8m, made by myself :( ).
What the meaning of 'jtag'? I didn't find the check box as you said. Which one? Button No.1 'Program'? Button No.5 'Configure'
Thanks again!
 

sof and pof 7128s

Jtag is a standard for talking directly to a chip or chain of devices.

If you have signals like TDI, TDO, TMS, TCK, ... then this is JTAG.

If so, make sure you DO NOT RUN the TDO cable next to the TCK cable. This is not self-evident at first, but look at this page and you'll understand...

https://www.ricreations.com/AppNote003.html

Big Boy
 

create pof file for cpld

Altera (And many other chip manufactures) provide the pins on their chips for a JTAG port which can be used for testing and programming of the chip. Quartus can use the JTAG port to program your chip, very useful for testing designs. The byte blaster normally would be connected to the JTAG port on your board, I think that you may need a .sof file to program your chip.

the POF file is used to program a serial config chip, if you are going to program your chip via JTAG then you need a .sof file. You need a Byteblaster II cable to program a serial config chip (I dont think you can use your MV) I am not famila with the details of the altera part you are using so I might be mistaken.
 

how i create a pof file from v project

mc_navman said:
@ltera (And many other chip manufactures) provide the pins on their chips for a JTAG port which can be used for testing and programming of the chip. qu@rtus can use the JTAG port to program your chip, very useful for testing designs. The byte blaster normally would be connected to the JTAG port on your board, I think that you may need a .sof file to program your chip.

the POF file is used to program a serial config chip, if you are going to program your chip via JTAG then you need a .sof file. You need a Byteblaster II cable to program a serial config chip (I dont think you can use your MV) I am not famila with the details of the @ltera part you are using so I might be mistaken.
Click to expand...

Thank you!
I am sorry, I don't understand the relation between POF file and the SOF file. I have no the license of quartus to compile VHDL and download the POF (or SOF) file to chip. So please tell me clearly in simple english, OK? Thank you!

To Big Boy, thank you! I have separate TDO and TCK, but no effect to be shown up. :(
 

read .pof files

When you compile a project in quartus it can generate several files for programming .sof and .pof are available. If you did not generate them at compile you can still use the convert program file utility built into quartus. Only one file type is suitable for programming a chip via the JTAG port. You should be able to gereate any file that you need. Can you detect your chip via the JTAG cable?

Also if you do not have a license for quartus you can get a free web license from @ltera.

You can contact your @ltera fae for more help. The came and showed me how to compile and program when I was getting started.
 

pof cpld

The serial download function will be blocked once any of those JTAG pins configed as IO. The only way to restore JTAG function is earse the whole chip using parallel programmer.

Regards,
 

tck tdi byteblaster cable length same

I have checked that a *.sof file is made by the Max plus II too. But when I push the download button, the *.pof file is automaticly loaded to the download window.
By the way, I did not define the JTAG pins as IO, let them blank.
 

ltera.com

HI..
I also faced the same problem in my project.... but after a long time i found very strange slution.... which is slight rise in VCCIO ( 3.3 or 5) on JTAG pins.... instead of 3.3 try to increase ur voltage max upto 3.5... and see the LED condition with byteblaster.....
first check whether LED indication with byteblaster is showing ready condition or not ????
ok probable solutions are
(1) check supply voltage properly at each pin of JTAG....
(2) have u connected pins according to datasheet ??
(3) what about pull up resistors ??
(4) according to ur CPLD/FPGA , whether it is SRAM/ROM based , u have to click on configer/rpogram and u have to use .pof for SRAM based chip and .sof for ROM based....
this list will be too big...
give me ur spec...i've done R&D in this thing..... my problem got solved after 3 months..and thats also ... by increasing VCCIO from 3.3 to 3.45.. so check ur current and voltage specs..
 

Re: HELP: Can't download *.pof file to my chip! (Altera CPLD

If you are sure all pin are connected correctly, you remember the ByteBlasterMV, work good if connected directly on parallel port, or which extension maximum 80 cm, and the extension must be do by hand yourself,
there are not cable in the market work correctly
regards
Maurizio
if you have do yourself the ByteBlaster, remember to use 74HC244, not
la or HCT
 

Re: HELP: Can't download *.pof file to my chip! (@ltera CPLD

jay_ec_engg said:
HI..
I also faced the same problem in my project.... but after a long time i found very strange slution.... which is slight rise in VCCIO ( 3.3 or 5) on JTAG pins.... instead of 3.3 try to increase ur voltage max upto 3.5... and see the LED condition with byteblaster.....
first check whether LED indication with byteblaster is showing ready condition or not ????
ok probable solutions are
(1) check supply voltage properly at each pin of JTAG....
(2) have u connected pins according to datasheet ??
(3) what about pull up resistors ??
(4) according to ur CPLD/FPGA , whether it is SRAM/ROM based , u have to click on configer/rpogram and u have to use .pof for SRAM based chip and .sof for ROM based....
this list will be too big...
give me ur spec...i've done R&D in this thing..... my problem got solved after 3 months..and thats also ... by increasing VCCIO from 3.3 to 3.45.. so check ur current and voltage specs..
Click to expand...

Thank you!
I will try the way you said. May it has a effect!

But my VCCIO is linked to 5V and VCCNT is linked to 3.3V, what can I do?
 

HELP: Can't download *.pof file to my chip! (@ltera CPLD)

I got this problem a long time ago. I can't download my program to CPLD 7128S through my office computer. But It's well work through myself's computer. I think the parallel port voltage is different. You can try to increase your parallel port voltage(just like use ICL7660) w24cxx.91i.net . I think it will solute this problem.
 

Re: HELP: Can't download *.pof file to my chip! (Altera CPLD

Have u checked " MULTI VOLT INTERFACE " ON ???in the option menu
U will get the this error message only if the cable can not recognize ur board ( JTAG ckt)... if ur very sure about the ckt design then check voltage levels... I am sure ther will be something wrong at that point. and if ur getting proper supply.. it may be a problem of a current....
As i suggested, try to increase VCCO of JTAG slightly. ( I think its 5V ) for u... then try to increase it to 5.1 or 5.15 and then try to blacnk check ur CPLD first..

check PAGE No-13 of this link
https://www.altera.com/literature/ds/m3000a.pdf

https://www.altera.com/literature/ds/dspghd.pdf , page-9

Hope this will help u....where r u from ?
 

Re: HELP: Can't download *.pof file to my chip! (Altera CPLD

hi,If you have not resovle the problem, I think I could give you a method to find the key. At first you should see whether the nconfig pin can be pull down by the download cable. This is the first the pace to start download. The specification of the time sequence please see the handbook of cpld.
 

HELP: Can't download *.pof file to my chip! (@ltera CPLD)

I think the Noise on TDO is too much that Jtag can't read the JTAG ID
 

Re: HELP: Can't download *.pof file to my chip! (Altera CPLD

Hi,
I had this problem with Altera FPGA devices. The problem was the parallel port on my Laptop could not handle the levels that the Altera ByteBlaster was creating.

We changed our ByeBlaster to ByteBlaster MV and it worked on all the laptops except for 2 Compaq computers.

If you can, add a pullup resistor on the TDO Signal, it can help you drive the signal to a level your computer can "read".

BR,
/Farhad
 

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