help Back end digital ASIC design

[Al Farouk]

I had made lot of design targeted it into FPGA, now I need help to target a design into ASIC one, what is the steps to do that. I can surrize the point that I do not know and the reply will be very appreciated
1- What should I get from the FAB. to target the design into its process.
2- What is the back end design steps, suppose that I use T@@ner tolls.
3- What is MWP (Multi wafer project ) and what organization support it.
4- what is the required design output to be submitted to the fab.

if any one can help with a tutorial it will help very much.

Regards

 

[eda_wiz]

1. You have to get the process libraries from the fab you are planning to use. Popular Fabs are TSMC , UMC , Chartered etc.. New libraries have dimensions 90nm , 130 nm etcc

2. Get the TSMC libraries first do a auto place and then optimize manually .. (donno much abt this)

3.. No Idea ..

4) layout file ...Usually GDSII format

 

[godsun]

MPW is cheap much more than Single chip Wafer.
because several company can share one wafer

 

[wadaye]

I had made lot of design targeted it into FPGA, now I need help to target a design into ASIC one, what is the steps to do that. I can surrize the point that I do not know and the reply will be very appreciated
1- What should I get from the FAB. to target the design into its process.
2- What is the back end design steps, suppose that I use T@@ner tolls.
3- What is MWP (Multi wafer project ) and what organization support it.
4- what is the required design output to be submitted to the fab.

if any one can help with a tutorial it will help very much.

Regards

3--- You mean is MPW, some foundry support MPW. You can contact

them. Such as SMICS, TSMC, CHARTER.

 

[Michael Chiang]

Hi,

MPW mean you could put different chip in one mask. The purpose is to save mask cost in the design debugging stage. Normally faundry site will provide this service.

 

[sudhirtj]

Hi Al Farouk,

1. All the Fab Process related files like Design Rule Document, GDSII Layer description files, Verification(DRC, LVS, ANTENNA) files, Technology Files(tool specific like cadence or synopsys or magma), Layout Parasitic Extraction files.

2. For the Backend Design you need the libraries(either from fab or from library vendor like Artisan, Nurlogic, VST......). The steps in the Backend Design are FloorPlanning, Placement, Clock Tree Synthesis, Routing.

3. MPW is usually done for prototyping. Here as others said the reticle cost, wafer cost are shared by different customers. Some fabs call this as Silicon Shuttle. I believe almost all fabs has calender for MPWs.

4. The final layout database in GDSII format is the final output to fab with DRC/ANTENNA report(optional) along with Tapeout request form which contains your process details(like single poly four metal 1P4M....., GDSII size/window, passivation opening.....) and the IP details used for the design.

-Sudhir

 

[hqqh]

Hi,

in the ebook section, i saw a book called "IC Design using L-Edit". But i can't find it now. i think this would be the right document to read.
but as i know l-edit is "only" for the last steps in ic design, before you have to synthesize your design for the target technology (using BuildGates (Cadence) or DesignCompiler (Synopsis)).
I'm not a expert to this topic. I try to learn the ic-design flow too.
So, please correct me, if i'm wrong.

greetings,
hqqh

 

[HCM_bucat]

1 get the cell library from Foundry, resynthesize with the library
2_Use Place and Route tool to PR the chip> Tanner is for Custom Layout if the chip is small you can do with Tanner, but it still take a long time
3 MOSIS is one of MWP in US
4 GDSII