Continue to Site

Welcome to

Welcome to our site! is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[HELP] ASIC Verification Interview [HELP]

Not open for further replies.


Newbie level 2
Jan 12, 2006
Reaction score
Trophy points
Activity points
asic verification interview

Hi all,

I have an interview coming up and the position deals with ASIC Verification.

My background:
Digital IC design, Analog IC design, VLSI, Digital Systems(VHDL, FPGAs). All are undergraduate courses.

The position is entry level:
ASIC Verification Engineer
-Own and create test plans, test infrastructure (test benches), and tests for ASIC simulation at the block and system levels, for pre-silicon simulation and/or post-silicon verification.
-Perform ASIC testing to ensure that ASIC functionality is to specification and performs as intended.
-Lead design reviews of your test plans, test benches, and/or tests.
-Participate in design reviews of others' IP modules, test plans, test benches, and/or tests as appropriate.
-Use of revision control techniques and tools to control any files you modify.
Use of bug-tracking tool to log and track failing tests and/or chip bugs.

During my phone conversation with the hiring manager, I was told the interview might deal with coding structure and she also mentioned that they use Specman E at work.
What kind of questions should I expect during the interview for this entry level position? Please post links to helpful sites. All help is greatly appreciated. :D

UPDATE 1: The job is in USA. Anyone who has been interviewed or conducts interviews in the verification field, please shed some light. Thank you all. :idea:

this book may be useful to you which describe how to use E to verfiy desgin.

Hi Veriguru,

I think as a fresh graduate, it is not much use to prepare yourself to answer technical question related to the requirement of the job. I think it is more important to demostrate a good understand and interest in the projects and subjects you had done in the school. Of course, this also depend on how experience is the interviewers.

When I interview a fresh-graduate, I am looking for qualities in the person that suit the job. Altitude and recommendation counts alot. Give 2 real examples:

1. A candidate did a sound analysis software project running on a PC. As part of the project, he also compile his C program on a DSP platform. The conclusion is that DSP run much slower than on a PC. When I ask him what is the different between a micro-processor and a DSP, he has no idea. This give me a bad impression.

2. A lecture (my friend) recommend me his student. The student is hard working and has good altitude. During interview, he could not answer most of the technical questions. However, his attempt to answer honestly (i.e. if you are not sure, say so). However, his positive altitude during the interview and is demostrate consistently in his pass project impress me.

I do not know the culture in your country. But I believe job-related knowledge is not so important during interview. The basic are.

Eng Han



even its for verification you should be sound on your basic.
doesnot matter which language they are using since you can do the verification using systemC,system Verilog or even using verilog.
get your fundamentals rightlook for C++ and how the verification methologies can be you have rtl to verify...make a model of same rtl in either of language(just capture the functionality) and apply same test vectors to both rtl and model and check .
actually verification is an art and its all depends upon you imagination.
so buddy focus on your fundamentals rather than begin lost in details and best of luck

Manmohan Singh

Not open for further replies.

Part and Inventory Search

Welcome to