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module bcd_count(clk, reset, ce, count);
input clk, reset;
input ce; // count enable
output [7:0] count; // two digit bcd counter
reg [7:0] count;
always @(posedge clk or posedge reset) begin
if (reset) begin
count <= 7'h00;
end else begin
if (ce)
if (count[3:0] == 9) begin
count[3:0] <= 0;
if (count[7:4] == 9)
count[7:4] <= 0;
else
count[7:4] <= count[7:4] + 1;
end else begin
count[3:0] <= count[3:0] + 1;
end
end // else: !if(reset)
end // always @ (posedge clk or posedge reset)
endmodule // bcd_count