multiplier gives x
I am doing homework about writing verilog code about signed multiplication.
I wrote a multiplier.v file and two submodule to do the 2's complement(twocmplement.v) and unsigned multiplication(mult_unsigned.v). but when i run the verilog, it says it can't find the definition about the twocomplement and mul_unsigned. Seems it can not call the two submodules. Anyone know if i can instantiate the sub-module like this? if not, how can i substatiate it? Thanks!
The main module is like this:
module mutiplier(a, b, p, sign);
input [3:0] a;
input [3:0] b;
output [7:0]
input sign;
wire [3:0] a1;
wire [3:0] b1;
wire [7:0] p1;
if (sign) begin//signed operation
case ({a[3], b[3]})
2'b00:
mult_unsigned c1 (.a_un(a), .b_un(b), .p_un(p1));
p=p1;
2'b10:
twocomplement c2 (.x(a), .z(a1));
mult_unsigned c3 (.a_un(a1), .b_un(b), .p_un(p1));
twocomplement c4 (.x(p1), .z(p));
2'b01:
twocomplement c5 (.x(b), .z(b1));
mult_unsigned c6 (.a_un(a), .b_un(b1), .p_un(p1));
twocomplement c7 (.x(p1), .z(p));
2'b11:
twocomplement c8 (.x(a), .z(a1));
twocomplement c9 (.x(b), .z(b1));
mult_unsigned c10 (.a_un(a1), .b_un(b1), .p_un(p1));
p=p1;
endcase
end
else //unsigned operation
mult_unsigned c5 (.a(a), .b(b), .p(p));
end
endmodule