help about multiplier verilog code..

[triquent]

multiplier gives x

I am doing homework about writing verilog code about signed multiplication.
I wrote a multiplier.v file and two submodule to do the 2's complement(twocmplement.v) and unsigned multiplication(mult_unsigned.v). but when i run the verilog, it says it can't find the definition about the twocomplement and mul_unsigned. Seems it can not call the two submodules. Anyone know if i can instantiate the sub-module like this? if not, how can i substatiate it? Thanks!
The main module is like this:
module mutiplier(a, b, p, sign);
input [3:0] a;
input [3:0] b;
output [7:0]
input sign;
wire [3:0] a1;
wire [3:0] b1;
wire [7:0] p1;

if (sign) begin//signed operation
case ({a[3], b[3]})
2'b00:
mult_unsigned c1 (.a_un(a), .b_un(b), .p_un(p1));
p=p1;
2'b10:
twocomplement c2 (.x(a), .z(a1));
mult_unsigned c3 (.a_un(a1), .b_un(b), .p_un(p1));
twocomplement c4 (.x(p1), .z(p));
2'b01:
twocomplement c5 (.x(b), .z(b1));
mult_unsigned c6 (.a_un(a), .b_un(b1), .p_un(p1));
twocomplement c7 (.x(p1), .z(p));
2'b11:
twocomplement c8 (.x(a), .z(a1));
twocomplement c9 (.x(b), .z(b1));
mult_unsigned c10 (.a_un(a1), .b_un(b1), .p_un(p1));
p=p1;
endcase
end
else //unsigned operation
mult_unsigned c5 (.a(a), .b(b), .p(p));
end
endmodule

 

[nand_gates]

illegal left-hand-side assignment verilog

Hi ,
You can not do instantiation inside if or case statements. Your code wont work.
Here I have corrected it....

module mutiplier(a, b, p, sign);
   input [3:0] a;
   input [3:0] b;
   output [7:0] p;
   input       sign;
   reg [3:0]   a1;
   reg [3:0]   b1;
   wire [7:0]  p1;

   mult_unsigned mult (.a_un(a1), .b_un(b1), .p_un(p1));
   
   always @(/*AS*/a or b or p1 or sign) begin
       a1 = a;
       b1 = b;
       p = p1;
       if (sign) //signed operation
         case ({a[3], b[3]})
             2'b10 : begin
                 a1 = ~a + 1;
                 b1 = b;
                 p = ~p1 + 1;
             end
             2'b01 : begin
                 a1 = a;
                 b1 = ~b + 1;
                 p = ~p1 + 1;
             end
             2'b11 : begin
                 a1 = ~a + 1;
                 b1 = ~b + 1;
                 p = p1;
             end
         endcase
   end // always @ (...
endmodule

But to do signed and unsigned integer multiplication you can use what is known as
Booth's algorithm you can search yahoo for that.

 

[triquent]

thank you very much! but i am still confused about several points.
1)why do you use reg for a1 and b1, but use wire for p1?
2) why use p1 in the sensitive list of always statement? will it give error when doing the synthesis?
3) in the case statement, you didn't give out the 2'b00 case. so when do the synthesis, it is not the full case. will this cause problem in the synthesis?
4)also only if statement and without else statement will cause latch when doing the synthesis.
5) maybe it is easier for me to write two functions or tasks(2'scomplement and unsigned_mult). then i can call the two functions as: a=twocomplement(a1) p=mult_unsgined(p1).

Hi ,
You can not do instantiation inside if or case statements. Your code wont work.
Here I have corrected it....

module mutiplier(a, b, p, sign);
   input [3:0] a;
   input [3:0] b;
   output [7:0] p;
   input       sign;
   reg [3:0]   a1;
   reg [3:0]   b1;
   wire [7:0]  p1;

   mult_unsigned mult (.a_un(a1), .b_un(b1), .p_un(p1));
   
   always @(/*AS*/a or b or p1 or sign) begin
       a1 = a;
       b1 = b;
       p = p1;
       if (sign) //signed operation
         case ({a[3], b[3]})
             2'b10 : begin
                 a1 = ~a + 1;
                 b1 = b;
                 p = ~p1 + 1;
             end
             2'b01 : begin
                 a1 = a;
                 b1 = ~b + 1;
                 p = ~p1 + 1;
             end
             2'b11 : begin
                 a1 = ~a + 1;
                 b1 = ~b + 1;
                 p = p1;
             end
         endcase
   end // always @ (...
endmodule

But to do signed and unsigned integer multiplication you can use what is known as
Booth's algorithm you can search yahoo for that.

 

[echo47]

twocmplement and mul_unsigned don't exist in the Verilog language.

Why don't you simply let the compiler do the hard work for you? (assumes Verilog 2001)

reg  signed [7:0]  a=123, b=-77;
wire signed [15:0] y = a * b;

Gives result -9471

 

[triquent]

actually i have a question for the instantiation. the verilog will excute the submodule mutl_unsigned first or will do the always block first to find the a1, b1 first.
still confused about how the code is run by the simulator.

 

[triquent]

we are not using the verilog 2001. and the verilog VHDL doesn't have built-in supported for signed arithmetic operation. the homework want us to write Verilog module that performs both signed and unsigned binary multiplication operations.

twocmplement and mul_unsigned don't exist in the Verilog language.

Why don't you simply let the compiler do the hard work for you? (assumes Verilog 2001)

reg  signed [7:0]  a=123, b=-77;
wire signed [15:0] y = a * b;

 

[khorram]

actually i have a question for the instantiation. the verilog will excute the submodule mutl_unsigned first or will do the always block first to find the a1, b1 first.
still confused about how the code is run by the simulator.

The submodule and always block will run concurrently. If one of parameters in the submodule activates, the submodule runs. If one of variables in the sensitivity list of always block activates, the always block will run.

thank you very much! but i am still confused about several points.
1)why do you use reg for a1 and b1, but use wire for p1?
2) why use p1 in the sensitive list of always statement? will it give error when doing the synthesis?
3) in the case statement, you didn't give out the 2'b00 case. so when do the synthesis, it is not the full case. will this cause problem in the synthesis?
4)also only if statement and without else statement will cause latch when doing the synthesis.
5) maybe it is easier for me to write two functions or tasks(2'scomplement and unsigned_mult). then i can call the two functions as: a=twocomplement(a1) p=mult_unsgined(p1).

Whenever you want to use a variable as input, you declare it as wire. If you want to use a variable as output you should declare it as reg.

Regards,
KH

 

[nand_gates]

1)why do you use reg for a1 and b1, but use wire for p1?
-> Inside always block you can assign values to only reg types.

2) why use p1 in the sensitive list of always statement? will it give error when doing the synthesis?
-> Because its getting assined to reg p; No error will be generated for synthesis.

3) in the case statement, you didn't give out the 2'b00 case. so when do the synthesis, it is not the full case. will this cause problem in the synthesis?
-> This is the normal style used in combo block description it wont be a problem for
synthesis tool.

4)also only if statement and without else statement will cause latch when doing the synthesis.
-> No! Because at the begining only I have assigned default values to a1, b1 and p.

5) maybe it is easier for me to write two functions or tasks(2'scomplement and unsigned_mult). then i can call the two functions as: a=twocomplement(a1) p=mult_unsgined(p1).
-> OK!

 

[triquent]

I tried your code. but the I got errors. said "Illegal left-hand-side assignment for p1=p, p=~p1+1..." seems only p pin got problems. The a, a1, b, b1 are ok. Still still figure out the problems.

1)why do you use reg for a1 and b1, but use wire for p1?
-> Inside always block you can assign values to only reg types.

2) why use p1 in the sensitive list of always statement? will it give error when doing the synthesis?
-> Because its getting assined to reg p; No error will be generated for synthesis.

3) in the case statement, you didn't give out the 2'b00 case. so when do the synthesis, it is not the full case. will this cause problem in the synthesis?
-> This is the normal style used in combo block description it wont be a problem for
synthesis tool.

4)also only if statement and without else statement will cause latch when doing the synthesis.
-> No! Because at the begining only I have assigned default values to a1, b1 and p.

5) maybe it is easier for me to write two functions or tasks(2'scomplement and unsigned_mult). then i can call the two functions as: a=twocomplement(a1) p=mult_unsgined(p1).
-> OK!

 

[jelydonut]

problem with p is that no register was declaired for that assignment..

add..,.

reg [7:0] p;


jelydonut

 

[triquent]

Hi, guys. I tried to write it in the following ways now. i wrote two submodules (to do the 2's complement). but when the a or b or both is negative and need to do the 2's complement, then p will get zero. if both a and b is positive, then the result will be ok. seems the p=a1*b1 won't get any value a1 or b1. there is a dealy proble. anyone has suggestions to make it work? thanks!




module multiplier(a, b, p, sign);
parameter a_size=4;
parameter b_size=4;
parameter p_size=8;
input [a_size-1:0] a; //multiplicand
input [b_size-1:0] b; //multiplier
output [p_size-1:0] p; //product
reg [p_size-1:0] p;
input sign;
wire [a_size-1:0] a1;
wire [b_size-1:0] b1;
wire [p_size-1:0] p1;

twocomplement1 c1 (.x(a), .z(a1));

twocomplement1 c2 (.x(b), .z(b1));

twocomplement2 c3 (.x(p), .z(p1));

always @(/*AS*/a or b or sign) begin
if (sign) //signed operation
case ({a[a_size-1], b[b_size-1]})
2'b00 :
p = a * b;
2'b10 : begin
p = a1 * b;
p = p1;
end
2'b01 : begin
p = a * b1;
p = p1;
end
2'b11 :
p = a1 * b1;
endcase
else //unsigned operation
p = a * b;
end // always @ (...
endmodule

 

[nand_gates]

One correction in my code you need to declair "p" as "reg" type.
add this to code and it will work
Here is the corrected code

module mutiplier(a, b, p, sign);
   input [3:0] a;
   input [3:0] b;
   output [7:0] p;
   input       sign;
   reg [7:0]   p;
   reg [3:0]   a1;
   reg [3:0]   b1;
   wire [7:0]  p1;

   mult_unsigned mult (.a_un(a1), .b_un(b1), .p_un(p1));
   
   always @(/*AS*/a or b or p1 or sign) begin
       a1 = a;
       b1 = b;
       p = p1;
       if (sign) //signed operation
         case ({a[3], b[3]})
             2'b10 : begin
                 a1 = ~a + 1;
                 b1 = b;
                 p = ~p1 + 1;
             end
             2'b01 : begin
                 a1 = a;
                 b1 = ~b + 1;
                 p = ~p1 + 1;
             end
             2'b11 : begin
                 a1 = ~a + 1;
                 b1 = ~b + 1;
                 p = p1;
             end
         endcase
   end // always @ (...
endmodule