help a beginner out (Multi-source in unit <converter>

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multi-source in unit verilog

Hello, I am just beginning to learn Verilog, and am using ISE 10.1.
I am trying to make a custom color converter based on my own table, but am getting the following errors:
Multi-source in unit <converter> on signal <out_rgb<11 to 0>>; this signal is connected to multiple drivers.

could you guys help me in the right direction? Thanks!

Code: 
module converter(clk, colorin, out_rgb);
	input clk;
	input [11:0] colorin;
	output [11:0] out_rgb;
	reg [11:0] out_rgb;
	reg [11:0] rgb;

	always @ (clk or colorin)
	begin
			case (colorin)
			12'h000: rgb <= 12'b010101010101;
			12'h001:	rgb <= 12'b000000000000;
			12'h002:	rgb <= 12'b000000001000;
			12'h003:	rgb <= 12'b001000000111;
			...
			12'h30F:	rgb <= 12'b000000000000;
			default: rgb <= 12'b000000000000;
			endcase
	end

	always @ (clk or out_rgb)
	begin
		out_rgb2 <= out_rgb;
	end
endmodule
 

verilog multi-source in unit

Few hints :

1. Inthe first and second always block why are using clk in the sensitivity list if you are not using, remove it.

2.out_rgb is a o/p according to u r interface and is declared as reg. is this u r complete code, how are you generating your out_rgb. if you dont put the complete code, its hard to understand the problem. u have also used out_rgb2 which gets the value of out_rgb but declared in the code. put the complete code so that its easy to find your problem.
 

this signal is connected to multiple drivers

Whoops, I copy and pasted the wrong parts, this is what it should look like. Also, i need a conversion done per clock cycle, thats why I put the clk in the sensitivity list?

Code: 
module converter(clk, colorin, out_rgb); 
   input clk; 
   input [11:0] colorin; 
   output [11:0] out_rgb; 
   reg [11:0] out_rgb; 
   reg [11:0] rgb; 

   always @ (clk or colorin) 
   begin 
         case (colorin) 
         12'h000: rgb <= 12'b010101010101; 
         12'h001:   rgb <= 12'b000000000000; 
         12'h002:   rgb <= 12'b000000001000; 
         12'h003:   rgb <= 12'b001000000111; 
         ... 
         12'h30F:   rgb <= 12'b000000000000; 
         default: rgb <= 12'b000000000000; 
         endcase 
   end 

   always @ (clk or rgb) 
   begin 
      out_rgb <= rgb; 
   end 
endmodule
 

multi-source in unit on signal

module converter(clk, colorin, out_rgb);
input clk;
input [11:0] colorin;
output [11:0] out_rgb;
wire[11:0] out_rgb;
reg [11:0] rgb;

always @ (posedge clk)
begin
case (colorin)
12'h000: rgb <= 12'b010101010101;
12'h001: rgb <= 12'b000000000000;
12'h002: rgb <= 12'b000000001000;
12'h003: rgb <= 12'b001000000111;
...
12'h30F: rgb <= 12'b000000000000;
default: rgb <= 12'b000000000000;
endcase
end


assign out_rgb = rgb;

endmodule

may be this is what u want. Let me know if it works.
 

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