[SOLVED] HDLParsers:164 - Line 81. parse error, unexpected IDENT expecting SEMICOLON

[chaitanya.531]

Hey Folks,
plz
Need a little help here with my VHDL code.

I'm new to VHDL so please bear with me.

I'm getting the following Error messages for my code posted below. (I'm using the xilinx 8.1.03i and modelsim )
ERROR:HDLParsers:164 - "C:/Xilinx/rcc3/fgh/test.vhd" Line 81. parse error, unexpected IDENTIFIER, expecting SEMICOLON

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use STD.TEXTIO.all;
use IEEE.STD_LOGIC_TEXTIO.all;

ENTITY test_vhd IS
generic (      T        : time   := 10 ns ;
              keyfile   : string := "C:\Xilinx\rcc3\fgh\rc5.key" );
END test_vhd;

ARCHITECTURE behavior OF test_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT rc5round
	PORT(
		si : IN std_logic_vector(32 downto 1);
		di : IN std_logic_vector(64 downto 1);
		encdec : IN std_logic;
		data_in : IN std_logic;
		clk : IN std_logic;          
		do : OUT std_logic_vector(64 downto 1)
		);
	END COMPONENT;

	--Inputs
	SIGNAL encdec :  std_logic := '0';
	SIGNAL data_in :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL si :  std_logic_vector(32 downto 1) := (others=>'0');
	SIGNAL di :  std_logic_vector(64 downto 1) := (others=>'0');
     
	--Outputs
	SIGNAL do :  std_logic_vector(64 downto 1);
   -- files and constatnts
   file kfp : text open read_mode  is keyfile;
   CONSTANT clk_period : time := 10 ns;
   constant D : time := 10 ns; 
BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: rc5round PORT MAP(
		si => si,
		di => di,
		do => do,
		encdec => encdec,
		data_in => data_in,
		clk => clk
	);
 
	clk_process :PROCESS
   begin
        clk <= '0';
        wait for clk_period/2; 
        clk <= '1';
        wait for clk_period/2; 
   end process;
   
    -- process to set up subkeys
  subky:  process
          variable L : line;
          variable bv1 : std_logic_vector(32 downto 1);
          begin
          data_in <= '1' after 1ns;
          wait for 9*T;
          data_in <= '0' after 1ns ;
              for i in 0 to 26-1 loop
          readline(kfp,L); -- read subkey from file
          read(L,bv1);
          wait until rising_edge(clk);
              si <= bv1 after D; -- sen to rc5 top
          end loop;
          wait until rising_edge(clk);
          data_in  <= '0' after D;
          wait; -- halt this process
    
          end process;
   	tb : PROCESS
	BEGIN
     wait for 100ns 
      encdec <= '0';
      di<= x"c737c3a98e9b6f9b"; 
		wait;
	END PROCESS;

END;

this is test bench of a program

 

[ravics]

I think you missed a semicolon at line 80

  wait for 100ns[B];[/B]

 

[chaitanya.531]

I think you missed a semicolon at line 80

  wait for 100ns[B];[/B]

error rectified
thank u