HDL Entry vs. Schematic Entry Tool?

[AaronDu]

I use VHDL , because it is popular ouside my country , but verilog is popular in my country , so use it sometime

 

[Zerox100]

I use Vhdl and verilog both. It is better than schematic.

 

[CatKing]

No No No
Sch entry will never die enev all of you guys use HDL, because most of Analog circuits design must use sch entry, not HDL.
Analog HDL (Verilog-A or VHDL-AMS) may be do some work during analog design phase, but modeling and simualtion only, you HAVE TO do sch drawing until transistor level(SPICE) simulation finished.

 

[ted]

I have to agree that the needs (and therefore best tools) are quite different for analog and digital designs. I design mostly digital circuitry, specially the ones to be put onto a chip, and VHDL is a good tool.

On the other hand, I design also some analog circuitry (on board level!), and there I could not imagine to use a text based tool. Schematics is much more natural. I have not tried Verilog-A nor VHDL-AMS, but I am a bit suspicious regarding their generality :wink:

I am pretty sure that in a chip level mixed design some blocks might be best to enter by schematics entry (the analog ones) and most of the digital in HDL.

Ted

 

[joe2moon]

HDL + Schematic complete the design !

Dear all:

HDL-entry and schematic-enrty do not contradict each other !

No matter ASIC or FPGA,
you can use HDL to implement the sub-modules.,
and use schematic to integrate them at higher level.

 

[ddt694]

I agree with joe2moom!!!
HDL-entry will never replace SCH-entry.

 

[ddt694]

I use HDL-entry to implement sub-modules and some complicated control modules.

I do use SCH-entry to implement the top
level design or some sub-molules.

 

[ddt694]

I never use HDL-entry to implement the
top level design

 

[geconom]

Like reported in the later posts, I use HDLs (mainly VHDL) for submodules and either schematics or HDLs for interconnections and top level design. Sometimes, schematics are required for documentation or to present your ideas to other group members. However, I like tools like Mentor HDL-Designer, which let you have a complete view of the system as HDL and do not hide any parts. Otherwise, I can not understand what is going during simulation.

 

[skyglider]

Both VHDL and schematic

VHDL for a blocks description and schematics at the top level

 

[it_boy]

I use Verilog, using schematics it may probably take me years for what I have designed in HDL

 

[mike]

The concept of HDL entry and Schematic is equivalent, but HDL entry is more popular nowaday. However, the final gate count for Schematic may be smaller than that of HDL entry. If the synthesizer is good enough, than no one will use schematic entry. Anyway the concept of logic design should be consistent.

 

[YUV]

However, the final gate count for Schematic may be smaller than that of HDL entry.

It can be so, when you made behavioral description and have a weak synthesizer. But in the case of structural description you'll have no differences.
The synthesizer doesn't process schematics directly. IMHO it converts schematics into something like HDL.

 

[Ohh2]

In general, I don't use Schematic entry tools. But for some cases, using schematic tools to capture structure of a circuit (a regular datapath) may be useful.

 

[shekar_vlsi]

I will go with HDL entry b'cos there is no need to know the gate level architecture of the design

 

[sp]

my experience was i hate learn coding ...

so i used schematic for doing the digital design... i was doing the state machine.... i draw the state diagram (state/next state), do K-map for optimizing....... and i gave up... doing 10 states was allready making me crazy on the K-map.... so many errors... so i quit..

then i start to learn HDL (VHDL)... it is interesting... it can represent the FSM so easily n the compiler do all the jobs.... i just focus on my behaviour design part... i love it...

however, the bitter experience is very important... i learn all the required digital logic fundamental, n i see hardware whenever i write HDL... this is the most important part of writing HDL....(like the ONE sees the binary streams in the Matrix world???...)

visualize the hardware in HDL is the most important part in writting effective HDL...

it is just my own experence...

regards,
sp

 

[Alvinnju]

hi
i use Verilog,i think it's more easy

 

[mixel]

I think the combinational approach is the best, I describe different functional blocks with VHDL or AHDL and assemble whole system with Schematic Entry Tool...

 

[echo47]

For many years I designed signal processing systems with Xilinx 4000 series FPGAs using schematic capture and XACT tools. A few years ago I switched to Virtex II devices and Verilog. It took me only a few days to learn Verilog well enough to design FPGAs at least ten times faster than before.

 

[rajsrikanth]

i use xilinx for everything and. and at the most 1 percent i use schmatic .