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HDL Entry vs. Schematic Entry Tool?

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Full Member level 2
Jan 16, 2002
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What Entry tool you recomeds or use?
I'm not interesting about advantages or disadvantages in 1st or 2nd case!!!
I'm interesting how much ppl are using VHDL or Verilog, and how much - Schematic entry tool...

be well,
Wazard Dreamer

Hi wzdreamer,

I have it very clear, HDL Entry.

Then you can go for VHDL or Verilog, enterely up to you. My advice is VHDL as you know there are pros/contras for VHDL and pros/contras for Verilog.

- Maestor


I use VHDL. The choice was made for the availability of tools.

I’m using verilog. Schematic entry is a thing of the past.


i think taht today is available only the vhdl tools.
In past i preferred the schematic entry.
whne the devices are too big is really difficult to manage a schematic entry.
Xilinx is a example how to a tool can grow worse. in foundation 3.1 the schematic entry was really nice.
in ise is a shit.


ok :))) there aren't ppl, who uses Schematic...
Schematic is dead :pPPppp

I use VHDL. When I was first learning I used schematic for about a week.

I use VHDL, dictated by the company. Use to use schematic with x1linx foundation, and max+ few years back.

ECS (the tool in Xilinx'ISE for sch design entry) is so bad!
maxplus2's sch tool is good.and Viewdraw is great!

There is no doubt that VIEWDRAW is great for schematic entry design. But future is only VHDL or VERILOG based designs. It is just because of portability of the code for different target FPGAs of different vendors.


Like all the others, I use mainly HDL entry.


I have used schematics entry for some old Xilinx chips VERY many years ago. I guess that would be still useful for some simple and small designs, but schematics is imho not a way to go today.

I use mostly VHDL for FPGAs, and have used a littel Altera's AHDL, too. For smaller projects I have earlier designed Lattice's CPLD's with Abel, and small PLDs with CUPL.

In all cases, I feel text based tools have been best for chip level design. The PCB level design is another story....



i use verilog. i think it is easier to learn and grasp than VHDL

We are switching to HDL based design due to portability problems. However I still like the graphical representation of the top level design. For this we arecurrently using Synplify with "HDL analyst" which generates block diagrams for the synthesized design.

Our decision on switching to HDL(VHDL in our case) is based on the hurdles we had to live through when Xilinx broke backwards compatibility of their schematics tools.

We are using ALDEC as the simulation tool. Sometimes we use code-to-graphics feature to identify connectivities for blocks. But almost all of the designs are in VHDL.

I should say there is still a resistance in our company (mainly old folks) to switch over to VHDL.

if it is digital design then it is HDL and if it is analog design then it is schematic entry

verilog easy and more comfortable and requires less coding compared to VHDL

Few year ago I used schematic entry, but now I use only VHDL entry.

HDL is better because you can easily introduce new tools into your flow.
Verilog is supported by more tools then VHDL, because it usually used for ASIC design.

I used to swear by my schematic entry tools, but I'm a firm VHDL convert now. The escalating complexity of both devices and designs means that schematic entry is no longer an efficient method of design - the abstraction of an HDL is neccesary. Just like you won't find many people programming windows applications in assembler, the complexity of the problems means that we have to move away from thinking about the little details (leave that to the compiler/synthesiser) and focus on the bigger issues...


I use verilog entry, because I lerarned C++ and it's very easy for me to grasp verilog.


When i use fpga or cpld, i don't use schematic, because, Xilinx, for example, doesn't compatible with different version of them software.
I prefere tu use ABEL, but engenieer of Xilinx disapprove my choice, because for them, this langage is too old and not make for new big chip.
So i begin to use VHDL

Good luck

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