Yongchan
Newbie level 1
Have you ever done timing simulation with ARM standard cell library, especially full adder ?
There are 3 inputs (A,B,CI), 2 outputs (CO,S) for the full adder and it looks like missing specify statements for them.
When CI == 0, A == 1, B == 1, the outputs should be CO = 1, S = 0. And when A,B fall, CO also falls to 0.
If there is some delay between A and B falling time, CO has some output delay (SDF annotated or default delay).
But if A and B fall at the same, CO has no output delay!. Is that normal ?
Every full adder in ARM standard cell libraries has the same specify description.
In my case, it causes Hold violation. But in STA, there is no problem.
Anybody has the same experience ?
Thanks in advance.
There are 3 inputs (A,B,CI), 2 outputs (CO,S) for the full adder and it looks like missing specify statements for them.
When CI == 0, A == 1, B == 1, the outputs should be CO = 1, S = 0. And when A,B fall, CO also falls to 0.
If there is some delay between A and B falling time, CO has some output delay (SDF annotated or default delay).
But if A and B fall at the same, CO has no output delay!. Is that normal ?
Every full adder in ARM standard cell libraries has the same specify description.
In my case, it causes Hold violation. But in STA, there is no problem.
Anybody has the same experience ?
Thanks in advance.