I did never see any guidelines.
What I always used were few basic rules:
a) vertical size of all cells must be the same, would be nice if horizontal size are integer multiples of the min x (usualy min inverter)
b) VDD/VEE bus must be shared just by abuttment of the cells (the only metal going to the very edge of the cell)
c) use Met1 and Poly for routing not to block routing space above. If needed Met2 but as little as possible. (this sure depends for what speed you are designing)
d) all layer has to have at least min spacing from the edge of the cell not to violate DRC when butting them together.
e) each cell has to have its own well and substrate ties
f) I personaly do not like special I/O vias and "landing" structures because those usualy are not useful during final layout - in my opinion they cause more harm then anything else.
g) create filler cells 1x,2x,3x,4x.5x of min horizontal min size.
As you seen those are common sense practices but those surprisigly work....