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The concept of gradual sizing is called Logical effort.. this can be applied to all gates provided they are properly constructed with basic inverter characterized. search Google for logical effort+ stanford handout. u will find a good lecture pdf on the topic. the gradual sizing optimizes power delay product.
As a rule for least wasted power, you want to get
through the linear region of the inverter gate quickly.
At an insanely high taper ratio you will spend a lot of
time with high shoot-through current because your
predecessor stage was unable to swing the gates
(N+P) quickly.
At an insanely low taper ratio, you will have many
more stages than necessary and at some point
the simple excess capacitance costs more than
you gain from driving down shoot-through. 1:1
taper means you never gain current drive so that
is the "brick wall of stupid".
In between is where you search for your happy
place. I've seen it said that 1:3 is the best for
prop delay in logic clock tapers, but I've had to
go as low as 1:2 when pushing the technology,
eat delay for edge-rate (400MHz main clock in
a 0.5um technology, boo yeah). On the other
hand in a power switch you don't really want half
your switch area eaten by predriver, but would
rather manage shoot-through by timing.
It is an easy concept....Just think only 1 person trying to push a truck...I takes heavy effort and energy(relate energy to requiered current), but if there are many people it takes lesser effort and energy...
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