# Global variables in Verilog

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#### lostinxlation

I need to find some way to define a global variable that can be accessed by multiple tasks in Verilog.

For example, this code allows task1 and task2 to access global variable, 'mem', if the said variable is not declared in task1 and task2.
Code:
reg [15:0] mem [0:1023];

task2;

The issue for me is I still need to declare 'mem' inside task1 and task2 so that other team member won't have any issues in compilation, but doing so makes 'mem' a local variable and it cannot be shared as a global variable.

Basically, I'm looking for the way to use a globally accessible variable which is also defined as a local variable inside the task.
If I can pass the variable as an argument between the tasks, it would work as I intend, but I don't know if it's possible to pass around the multi-dimensional variables as arguments(Probably not, I guess).

Does anyone have a good idea how to let multiple tasks share the variable that is declared as a local variable in the tasks ?

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