er.akhilkumar
Full Member level 2
When I am elaborating the design following error has been reported:
ncelab: *E,CUNOTB: component instance is not fully bound (tb_top_asic.i_dut_top@dut_top(struct):i_dig_core@dig_core(rtl):i_wb_cr@wb_cr(rtl):i_cr816_top_1) [File:wb_cr.vhd, Line:222].
When I used -relax with ncelab command it shows following warning:
ncelab: *E,CUCGNA: component generic CR816_TOP.LAST_PC not associated with any formal [5.2.1.2].
Default binding for instance: tb_top_asic.i_dut_top@dut_top(struct):i_dig_core@dig_core(rtl):i_wb_cr@wb_cr(rtl):i_cr816_top_1
ncelab: *E,CUCPNA: component port CR816_TOP.N_RESET not associated with any formal [5.2.1.2].
Default binding for instance: tb_top_asic.i_dut_top@dut_top(struct):i_dig_core@dig_core(rtl):i_wb_cr@wb_cr(rtl):i_cr816_top_1
ncelab: *W,CUDEFF: default binding failed for component instance (tb_top_asic.i_dut_top@dut_top(struct):i_dig_core@dig_core(rtl):i_wb_cr@wb_cr(rtl):i_cr816_top_1) with design unit (DESIGN.CR816_TOP:STRUCT) because of the above mentioned reason.
Following is the code of both wb_cr.vhd and cr816top.vhd:
Please provide a solution.
ncelab: *E,CUNOTB: component instance is not fully bound (tb_top_asic.i_dut_top@dut_top(struct):i_dig_core@dig_core(rtl):i_wb_cr@wb_cr(rtl):i_cr816_top_1) [File:wb_cr.vhd, Line:222].
When I used -relax with ncelab command it shows following warning:
ncelab: *E,CUCGNA: component generic CR816_TOP.LAST_PC not associated with any formal [5.2.1.2].
Default binding for instance: tb_top_asic.i_dut_top@dut_top(struct):i_dig_core@dig_core(rtl):i_wb_cr@wb_cr(rtl):i_cr816_top_1
ncelab: *E,CUCPNA: component port CR816_TOP.N_RESET not associated with any formal [5.2.1.2].
Default binding for instance: tb_top_asic.i_dut_top@dut_top(struct):i_dig_core@dig_core(rtl):i_wb_cr@wb_cr(rtl):i_cr816_top_1
ncelab: *W,CUDEFF: default binding failed for component instance (tb_top_asic.i_dut_top@dut_top(struct):i_dig_core@dig_core(rtl):i_wb_cr@wb_cr(rtl):i_cr816_top_1) with design unit (DESIGN.CR816_TOP:STRUCT) because of the above mentioned reason.
Following is the code of both wb_cr.vhd and cr816top.vhd:
Code:
--Code of wb_cr.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY wb_cr IS
PORT (
ck_sys : IN std_logic; -- system clock
en1 : IN std_logic; -- enable phase 1
en3 : IN std_logic; -- enable phase 3
reset : IN std_logic; -- reset (active high)
pm_miss : IN std_logic; -- Program memory miss.
-- wishbone interface
wb_ack_i : IN std_logic; --! acknowledge
wb_dat_i : IN std_logic_vector(7 DOWNTO 0); --! Wishbone input data
wb_cyc_o : OUT std_logic; --! cycle valid output
wb_adr_o : OUT std_logic_vector(15 DOWNTO 0); --! address bus output
wb_we_o : OUT std_logic; --! indicates write transfer
wb_stb_o : OUT std_logic; --! strobe output
wb_dat_o : OUT std_logic_vector(7 DOWNTO 0); --! output data BUS
halt : OUT std_logic; -- = 1 when in halt
event_n : IN std_logic_vector(1 DOWNTO 0); -- events
interrupt_n : IN std_logic_vector(2 DOWNTO 0) -- interrupts
);
END ENTITY wb_cr;
LIBRARY coolrisc,design;
USE coolrisc.wrappers_816_pkg.ALL;
USE coolrisc.utils_816_pkg.ALL;
ARCHITECTURE rtl OF wb_cr IS
SIGNAL n_reset : std_ulogic; -- [IN]
SIGNAL ec1 : std_logic; -- clock enable for phase 1
SIGNAL ec3 : std_logic; -- clock enable for phase 3
SIGNAL ck1 : std_ulogic; -- [IN]
SIGNAL ck3 : std_ulogic; -- [IN]
SIGNAL ck1_scan : std_ulogic; -- [IN]
SIGNAL ck3_scan : std_ulogic; -- [IN]
SIGNAL halt_state : std_ulogic; -- [OUT]
SIGNAL freq_out : freq_vector; -- [OUT]
SIGNAL pm_addr : pm_addr_vector; -- [OUT]
SIGNAL pm_inst : ir_vector; -- [IN]
SIGNAL dm_e : std_ulogic; -- [OUT]
SIGNAL dm_miss : std_ulogic; -- [IN]
SIGNAL read_nwrite : std_ulogic; -- [OUT]
SIGNAL dm_addr : dm_addr_vector; -- [OUT]
SIGNAL data_in : data_vector; -- [IN]
SIGNAL data_in_str : data_vector; -- [IN]
SIGNAL data_out : data_vector; -- [OUT]
SIGNAL n_event : std_ulogic_vector(1 DOWNTO 0); -- [IN]
SIGNAL n_interrupt : std_ulogic_vector(2 DOWNTO 0); -- [IN]
SIGNAL test_e : std_ulogic; -- [IN]
SIGNAL test_in : std_ulogic; -- [IN]
SIGNAL test_out : std_ulogic; -- [OUT]
SIGNAL scan_mode : std_ulogic; -- [IN]
SIGNAL clk : std_logic;
SIGNAL csn : std_logic;
SIGNAL addr : std_logic_vector(11 DOWNTO 0);
SIGNAL rom_q : std_logic_vector(21 DOWNTO 0);
SIGNAL rdmon : std_logic;
-- output
SIGNAL wb_ack : std_logic; --! normal termination
SIGNAL wb_cyc_nxt : std_logic; -- next WB cacle value
SIGNAL wb_stb_nxt : std_logic; -- next WB cacle value
SIGNAL wb_stb_o_i : std_logic; --! normal termination
--! type defining the WB states
TYPE t_states IS
(
S_IDLE,
S_TRANS,
S_LAST
);
--! current state of the wishbone wrapper
SIGNAL wb_fsm_state_cur : t_states;
--! next state of the wishbone wrapper
SIGNAL wb_fsm_state_nxt : t_states;
--SIGNAL cr_d_wbm_i : cr_d_wbm_i_type;
-- SIGNAL cr_d_wbm_o : cr_d_wbm_o_type;
SIGNAL tie_lo, tie_hi : std_logic;
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
COMPONENT prom_4096x22x16 IS
GENERIC (
PreloadFilename : string;
hexadecimal_romcode : boolean;
-- ---------------------------------------------
-- Other flags
-- ---------------------------------------------
TimingChecksOn : boolean;
Xon : boolean;
MsgOn : boolean;
InstancePath : string);
PORT (
clk : IN std_logic;
csn : IN std_logic;
addr : IN std_logic_vector(11 DOWNTO 0);
q : OUT std_logic_vector(21 DOWNTO 0);
rdmon : OUT std_logic);
END COMPONENT prom_4096x22x16;
--=============== Conversion functions =================--
-- From std_logic To std_ulogic
FUNCTION to_ul (s : std_logic) RETURN std_ulogic IS
VARIABLE v : std_ulogic;
BEGIN
v := std_ulogic(s);
RETURN v;
END;
-- From std_logic_vector To std_ulogic_vector
FUNCTION to_ul (s : std_logic_vector) RETURN std_ulogic_vector IS
VARIABLE v : std_ulogic_vector(s'range);
BEGIN
v := std_ulogic_vector(s);
RETURN v;
END;
-- From std_ulogic To std_logic
FUNCTION to_sl (s : std_ulogic) RETURN std_logic IS
VARIABLE v : std_logic;
BEGIN
v := std_logic(s);
RETURN v;
END;
-- From std_ulogic_vector To std_logic_vector
FUNCTION to_sl (s : std_ulogic_vector) RETURN std_logic_vector IS
VARIABLE v : std_logic_vector(s'range);
BEGIN
v := std_logic_vector(s);
RETURN v;
END;
BEGIN -- ARCHITECTURE rtl
-----------------------------------------------------------------------------
-- Basic values
-----------------------------------------------------------------------------
tie_hi <= '1';
tie_lo <= '0';
-----------------------------------------------------------------------------
-- CoolRisc Wrapper.
-----------------------------------------------------------------------------
ck1_scan <= '0';
ck3_scan <= '0';
ec1 <= (en1 AND NOT pm_miss AND NOT dm_miss);
ec3 <= en3;
ck1 <= ck_sys AND ec1;
ck3 <= ck_sys AND ec3;
test_in <= '0';
test_e <= '0';
scan_mode <= '0';
n_reset <= NOT(reset);
n_event <= NOT(to_ul(event_n));
n_interrupt <= NOT(to_ul(interrupt_n));
pm_inst <= to_ul(rom_q);
i_cr816_top_1 : cr816_top
--GENERIC MAP (
-- last_pc => 4)
PORT MAP (
n_reset => n_reset, -- [IN]
ck1 => ck1, -- [IN]
ck3 => ck3, -- [IN]
ck1_scan => ck1_scan, -- [IN]
ck3_scan => ck3_scan, -- [IN]
halt_state => halt_state, -- [OUT]
freq_out => freq_out, -- [OUT]
pm_addr => pm_addr, -- [OUT]
pm_inst => pm_inst, -- [IN]
dm_e => dm_e, -- [OUT]
dm_miss => tie_lo, -- [IN]
read_nwrite => read_nwrite, -- [OUT]
dm_addr => dm_addr, -- [OUT]
data_in => data_in, -- [IN]
data_out => data_out, -- [OUT]
n_event => n_event, -- [IN]
n_interrupt => n_interrupt, -- [IN]
test_e => test_e, -- [IN]
test_in => test_in, -- [IN]
test_out => test_out, -- [OUT]
scan_mode => scan_mode); -- [IN]
addr <= to_sl(pm_addr(11 DOWNTO 0));
csn <= '0';
clk <= ck_sys;
i_prom_4096x22x16_1 : prom_4096x22x16
GENERIC MAP (
PreloadFilename => "./code.hex",
hexadecimal_romcode => true,
TimingChecksOn => true,
Xon => true,
MsgOn => true,
InstancePath => "ROM")
PORT MAP (
clk => clk, -- [in]
csn => csn, -- [in]
addr => addr, -- [in]
q => rom_q, -- [out]
rdmon => rdmon); -- [out]
-- Normal termination signal
wb_ack <= wb_ack_i;
-- TODO: add the clocking strategy as for the CR.
-- purpose: Sequential part of the Wishbone master part
-- type : sequential
-- inputs : ck_sys, rst_n, wb_fsm_state_nxt
-- outputs: wb_fsm_state_cur
p_wb_fsm_seq : PROCESS (ck_sys, reset) IS
BEGIN -- PROCESS p_wb_fsm_seq
IF reset = '1' THEN -- asynchronous reset (active high)
wb_fsm_state_cur <= S_IDLE;
ELSIF falling_edge(ck_sys) THEN -- falling clock edge
wb_fsm_state_cur <= wb_fsm_state_nxt;
END IF;
END PROCESS p_wb_fsm_seq;
-- purpose: Combinatorial part of the Wishbone SM master part
-- type : combinational
-- inputs : wb_fsm_state_cur, wb_ack, wb_we_o, dm_e,
-- outputs: wb_cyc_nxt, wb_stb_nxt, wb_fsm_state_nxt
p_wb_fsm_cmb : PROCESS (wb_fsm_state_cur, wb_stb_o_i, wb_ack, dm_e, ec3, ec1) IS
BEGIN -- PROCESS p_wb_fsm_cmb
CASE wb_fsm_state_cur IS
WHEN S_IDLE =>
-- IDLE state
IF (dm_e = '1' and ec1 = '1') THEN
wb_fsm_state_nxt <= S_TRANS;
ELSE
wb_fsm_state_nxt <= S_IDLE;
END IF;
WHEN S_TRANS =>
-- Normal transfer
IF (dm_e = '1' AND wb_ack = '1') THEN
-- End of transaction
IF (ec3 = '1') THEN
-- Data arrived, just in time
wb_fsm_state_nxt <= S_IDLE;
ELSE
-- data arrived before latching ec3.
wb_fsm_state_nxt <= S_LAST;
END IF;
ELSE
wb_fsm_state_nxt <= S_TRANS;
END IF;
WHEN S_LAST =>
-- wait until ck3 arrives, then wait for next cycle.
IF (ec3 = '1') THEN
wb_fsm_state_nxt <= S_IDLE;
ELSE
wb_fsm_state_nxt <= S_LAST;
END IF;
WHEN OTHERS =>
wb_fsm_state_nxt <= S_IDLE;
END CASE;
END PROCESS p_wb_fsm_cmb;
-- TODO: add the gating strategy: System to be clocked as for the CR, excpet
-- when on S_TRANS, where the clock shall be continous, to speed up the
-- answer.
-- purpose: Latched registers on the SM
-- type : sequential
-- inputs : ck_sys, reset, wb_dat_i
-- outputs: data_in
p_wb_fsm_out: PROCESS (ck_sys, reset) IS
BEGIN -- PROCESS p_wb_fsm_out
IF reset = '1' THEN -- asynchronous reset (active high)
data_in_str <= (OTHERS => '0');
dm_miss <= '0';
wb_cyc_o <= '0';
wb_stb_o_i <= '0';
ELSIF falling_edge(ck_sys) THEN -- falling clock edge
IF (ec3 = '1' AND wb_ack = '0' AND dm_e = '1' AND wb_fsm_state_cur = S_TRANS) THEN
dm_miss <= '1';
ELSE
dm_miss <= '0';
END IF;
IF (wb_ack = '1' AND dm_e = '1' AND
read_nwrite = '1' AND wb_fsm_state_cur = S_TRANS) THEN
data_in_str <= std_ulogic_vector(wb_dat_i);
END IF;
IF (wb_fsm_state_nxt = S_TRANS AND dm_e = '1') THEN
wb_cyc_o <= '1';
wb_stb_o_i <= '1';
ELSE
wb_cyc_o <= '0';
wb_stb_o_i <= '0';
END IF;
END IF;
END PROCESS p_wb_fsm_out;
wb_we_o <= NOT read_nwrite;
wb_adr_o <= std_logic_vector(dm_addr);
wb_dat_o <= std_logic_vector(data_out);
wb_stb_o <= wb_stb_o_i;
data_in <= std_ulogic_vector(wb_dat_i) WHEN (wb_fsm_state_cur = S_TRANS) ELSE data_in_str;
-- data_in <= std_ulogic_vector(wb_dat_i);
-- dm_miss <= NOT (wb_ack AND wb_stb_o) WHEN wb_fsm_state_cur = S_TRANS ELSE '0';
END ARCHITECTURE rtl;
--cr816_top.vhd code
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY CoolRisc;
USE CoolRisc.ALL;
USE CoolRisc.utils_816_pkg.ALL;
LIBRARY design;
USE design.btl_pkg.ALL;
ENTITY cr816_top IS
-- GENERIC (
-- );
PORT(
res : IN std_logic; -- Reset (active high)
ck1 : IN std_logic; -- CR Ck1 (Free running)
ck3 : IN std_logic; -- CR Ck3 (Free running)
-- Gated clocks in Halt state
ck1_gate : OUT std_logic; -- CR Ck1 Gated/Stopped in Halt, [PD]M_Miss
ck3_gate : OUT std_logic; -- CR Ck3 Gated/Stopped in Halt, [PD]M_Miss
stop_ck1 : IN std_logic; -- Stop CR Ck1 clock (during [PD]M_miss or DM-to-NVM access)
do_halt : OUT std_logic; -- Halt: CR Request for Ck1/Ck3 gating
halt_state : OUT std_logic; -- CR Halt-State: Ck1/Ck3 gated
-- PM interface
pm_inst : IN std_logic_vector(pm_instr_w-1 DOWNTO 0); -- PM instruction
pm_addr : OUT std_logic_vector(pm_addr_w-1 DOWNTO 0); -- current PM address
-- DM Interface
dm_din : IN std_logic_vector(dm_data_w-1 DOWNTO 0); -- DM access data input bus
dm_out_f : OUT dm_out_t; -- DM access data output bus - Free running
dm_out_p : OUT dm_out_t; -- DM access data output bus - For Peripherals
-- Interrupts + events
int : IN std_logic_vector(cr_int_w-1 DOWNTO 0);
evnt : IN std_logic_vector(cr_evt_w-1 DOWNTO 0);
is_stack_almost_full : OUT std_logic -- 1 when the stack is Almost full (last_pc-1 level used)
);
END cr816_top;
--------------------------------------------------------------------------------
--
-- Architecture : struct
-- Entity : cr816_top
-- Description :
--
--------------------------------------------------------------------------------
ARCHITECTURE struct OF cr816_top IS
--=============== Conversion functions =================--
-- From std_logic To std_ulogic
FUNCTION to_ul (s: std_logic) RETURN std_ulogic IS
VARIABLE v: std_ulogic;
BEGIN
v := std_ulogic(s);
RETURN v;
END;
-- From std_logic_vector To std_ulogic_vector
FUNCTION to_ul (s: std_logic_vector) RETURN std_ulogic_vector IS
VARIABLE v: std_ulogic_vector(s'RANGE);
BEGIN
v := std_ulogic_vector(s);
RETURN v;
END;
-- From std_ulogic To std_logic
FUNCTION to_sl (s: std_ulogic) RETURN std_logic IS
VARIABLE v: std_logic;
BEGIN
v := std_logic(s);
RETURN v;
END;
-- From std_ulogic_vector To std_logic_vector
FUNCTION to_sl (s: std_ulogic_vector) RETURN std_logic_vector IS
VARIABLE v: std_logic_vector(s'RANGE);
BEGIN
v := std_logic_vector(s);
RETURN v;
END;
COMPONENT cr816
GENERIC(
-- number of the last (top) PC of the PC stack. PC stack will go from 1 to
-- last_pc
last_pc : NATURAL := 4
);
PORT(
n_reset : IN STD_ULOGIC; -- reset (active low)
ck1 : IN STD_ULOGIC; -- clocks
ck3 : IN STD_ULOGIC;
do_halt : OUT STD_ULOGIC; -- = 1 when halt instr. (no int ..)
freq_out : OUT freq_vector; -- freq code output
pm_e : OUT STD_ULOGIC; -- PM access enable
pm_miss : IN STD_ULOGIC; -- PM miss
pm_miss_ack : OUT STD_ULOGIC; -- PM miss acknowledgement
pm_addr : OUT pm_addr_vector; -- current PM address
pm_inst : IN ir_vector; -- PM instruction
dm_e : OUT STD_ULOGIC; -- DM access enable
dm_miss : IN STD_ULOGIC; -- DM miss
read_nwrite : OUT STD_ULOGIC; -- read (when 1) or write (when 0)
dm_addr : OUT dm_addr_vector; -- DM address
data_in : IN data_vector; -- DM access data input bus
data_out : OUT data_vector; -- DM access data output bus
status_e : OUT STD_ULOGIC;
status_out : OUT STD_ULOGIC_VECTOR(bit_in2 DOWNTO bit_ev0);
interrupt : IN STD_ULOGIC_VECTOR(2 DOWNTO 0);
evnt : IN STD_ULOGIC_VECTOR(1 DOWNTO 0);
is_stack_almost_full : OUT STD_ULOGIC -- 1 when the stack is Almost full (last_pc-1 level used)
);
END COMPONENT cr816;
COMPONENT cr_top_ck_gen
PORT (
res : IN std_logic;
ck1 : IN std_logic; -- CK1 - Free-running
ck3 : IN std_logic; -- CK3 - Free-running
stop_ck1 : IN std_logic; -- Stop Ck1 clock ([PD]M_miss or DM-to-NVM access)
do_halt : IN std_logic; -- Halt instruction decoded
halt_state : OUT std_logic; -- Halt state indication
ck1_gate : OUT std_logic; -- Gated CK1
ck3_gate : OUT std_logic -- Gated CK3
);
END COMPONENT cr_top_ck_gen;
COMPONENT status_reg
GENERIC (
width : natural := 5 -- Status register width
);
PORT(
res : IN std_logic;
reg_inp : IN std_logic_vector(width-1 DOWNTO 0);
ck1 : IN std_logic;
ck3 : IN std_logic;
-- Status from CoolRISC
status_e : IN std_logic;
status_out : IN std_logic_vector(width-1 DOWNTO 0);
-- Status register
status_reg : OUT std_logic_vector(width-1 DOWNTO 0)
);
END COMPONENT status_reg;
COMPONENT or_n
GENERIC (
width : natural := 2
);
PORT (
a : IN std_logic_vector(width-1 downto 0);
z : OUT std_logic
);
END COMPONENT or_n;
----------------------------------------------------------
-- High / Low Constant signals
----------------------------------------------------------
SIGNAL s_lo : std_logic;
SIGNAL s_hi : std_logic;
--===== Internal signals =====
SIGNAL ck1_i : std_logic;
SIGNAL ck3_i : std_logic;
SIGNAL ck1_g_i : std_logic; -- Gated CK1
SIGNAL ck3_g_i : std_logic; -- Gated CK3
-- CoolRISC outputs
SIGNAL res_n_ui : std_ulogic; -- Reset (active low)
SIGNAL ck1_gate_ui : std_ulogic;
SIGNAL ck3_gate_ui : std_ulogic;
SIGNAL do_halt_ui : std_ulogic;
SIGNAL status_e_ui : std_ulogic;
SIGNAL status_out_ui : std_ulogic_vector(4 DOWNTO 0);
SIGNAL pm_addr_ui : std_ulogic_vector(pm_addr_width-1 DOWNTO 0);
SIGNAL pm_inst_ui : std_ulogic_vector(ir_width-1 DOWNTO 0);
SIGNAL dm_addr_ui : std_ulogic_vector(dm_addr_width-1 DOWNTO 0);
SIGNAL dm_e_ui : std_ulogic;
SIGNAL dm_rd_ui : std_ulogic;
SIGNAL dm_dout_ui : std_ulogic_vector(data_width-1 DOWNTO 0);
SIGNAL dm_in_ui : std_ulogic_vector(data_width-1 DOWNTO 0);
SIGNAL stat_reg_ui : std_ulogic_vector(5-1 DOWNTO 0);
SIGNAL is_stack_almost_full_ui : std_ulogic;
-- Status register
SIGNAL stat_inp_li : std_logic_vector(5-1 DOWNTO 0);
SIGNAL stat_reg_li : std_logic_vector(5-1 DOWNTO 0);
SIGNAL status_e_li : std_logic;
SIGNAL status_out_li : std_logic_vector(4 DOWNTO 0);
-- Gated clocks
SIGNAL do_halt_li : std_logic;
SIGNAL halt_state_li : std_logic;
SIGNAL ck1_gate_li : std_logic;
SIGNAL ck3_gate_li : std_logic;
SIGNAL dm_e_li : std_logic;
SIGNAL dm_addr_li : std_logic_vector(dm_addr_full_w-1 DOWNTO 0);
SIGNAL pm_addr_li : std_logic_vector(pm_addr_w-1 DOWNTO 0);
SIGNAL peri_range_n : std_logic;
--------------------------------------------------------------------------------
-- Begin
--------------------------------------------------------------------------------
BEGIN
s_lo <= '0';
s_hi <= '1';
--------------------------------------------
-- Type conversion (std_logic* <-> std_ulogic*)
--------------------------------------------
-- CoolRISC inputs conversion
res_n_ui <= NOT(to_ul(res));
ck1_gate_ui <= to_ul(ck1_gate_li);
ck3_gate_ui <= to_ul(ck3_gate_li);
pm_inst_ui <= to_ul(pm_inst);
dm_in_ui <= to_ul(dm_din);
stat_reg_ui <= to_ul(stat_reg_li);
-- CoolRISC outputs conversion
do_halt_li <= to_sl(do_halt_ui);
pm_addr_li <= to_sl(pm_addr_ui)(pm_addr_w-1 DOWNTO 0);
status_e_li <= to_sl(status_e_ui);
status_out_li <= to_sl(status_out_ui);
--------------------------------------
-- CR816 Core
--------------------------------------
i_cr816 : cr816
GENERIC MAP(
last_pc => cr_last_pc -- (natural)
)
PORT MAP(
n_reset => res_n_ui, -- (IN)
ck1 => ck1_gate_ui, -- (IN)
ck3 => ck3_gate_ui, -- (IN)
do_halt => do_halt_ui, -- (OUT)
freq_out => OPEN, -- (OUT)
pm_e => OPEN, -- (OUT)
pm_miss => s_lo, -- (IN)
pm_miss_ack => OPEN, -- (OUT)
pm_addr => pm_addr_ui, -- (OUT)
pm_inst => pm_inst_ui, -- (IN)
dm_e => dm_e_ui, -- (OUT)
dm_miss => s_lo, -- (IN)
read_nwrite => dm_rd_ui, -- (OUT)
dm_addr => dm_addr_ui, -- (OUT)
data_in => dm_in_ui, -- (IN)
data_out => dm_dout_ui, -- (OUT)
status_e => status_e_ui, -- (OUT)
status_out => status_out_ui, -- (OUT)
interrupt => stat_reg_ui(4 DOWNTO 2), -- (IN)
evnt => stat_reg_ui(1 DOWNTO 0), -- (IN)
is_stack_almost_full => is_stack_almost_full_ui -- (OUT)
);
-- pragma translate_off
check_cr_instr:
PROCESS (ck3_gate_ui)
BEGIN
IF (ck3_gate_ui'EVENT AND ck3_gate_ui = '0') THEN
ASSERT NOT(is_X(pm_inst_ui) AND (res_n_ui = '1'))
REPORT "ERROR: Invalid CoolRisc Instruction Latched."
SEVERITY ERROR;
END IF;
END PROCESS check_cr_instr;
-- pragma translate_on
--------------------------------------
-- Halt clock
--------------------------------------
i_cr_top_ck_gen : cr_top_ck_gen
PORT MAP(
res => res, -- (IN)
ck1 => ck1, -- (IN)
ck3 => ck3, -- (IN)
stop_ck1 => stop_ck1, -- (IN)
do_halt => do_halt_li, -- (IN)
halt_state => halt_state_li, -- (OUT)
ck1_gate => ck1_gate_li, -- (OUT)
ck3_gate => ck3_gate_li -- (OUT)
);
--------------------------------------
-- Status register
--------------------------------------
-- Status reg. input = Interrupt + Event vector
stat_inp_li <= int & evnt;
i_status_reg : status_reg
GENERIC MAP (
width => 5 -- (natural)
)
PORT MAP(
res => res, -- (IN)
reg_inp => stat_inp_li, -- (IN)
ck1 => ck1_gate_li, -- (IN)
ck3 => ck3_gate_li, -- (IN)
status_e => status_e_li, -- (IN)
status_out => status_out_li, -- (IN)
status_reg => stat_reg_li -- (OUT)
);
--------------------------------------
-- DM Output Buses
--------------------------------------
dm_addr_li <= to_sl(dm_addr_ui);
dm_e_li <= to_sl(dm_e_ui);
dm_out_f.e <= dm_e_li;
dm_out_f.addr <= dm_addr_li;
dm_out_f.rd <= to_sl(dm_rd_ui);
dm_out_f.dout <= to_sl(dm_dout_ui);
dm_out_p.rd <= to_sl(dm_rd_ui);
dm_out_p.dout <= to_sl(dm_dout_ui);
dm_addr_proc:
PROCESS (dm_addr_li)
BEGIN
dm_out_p.addr <= (OTHERS => '0');
dm_out_p.addr(dm_addr_w-1 DOWNTO 0) <= dm_addr_li(dm_addr_w-1 DOWNTO 0);
END PROCESS dm_addr_proc;
i_or_n: or_n
GENERIC MAP (
width => dm_addr_full_w - dm_addr_w -- (natural)
)
PORT MAP (
a => dm_addr_li(dm_addr_full_w-1 DOWNTO dm_addr_w), -- (IN)
z => peri_range_n -- (OUT)
);
dm_e_peri_proc:
PROCESS (dm_e_li, peri_range_n)
BEGIN
IF (peri_range_n = '0') THEN
dm_out_p.e <= dm_e_li;
ELSE
dm_out_p.e <= '0';
END IF;
END PROCESS dm_e_peri_proc;
--------------------------------------
-- Output assignement
--------------------------------------
ck1_gate <= ck1_gate_li;
ck3_gate <= ck3_gate_li;
do_halt <= do_halt_li;
halt_state <= halt_state_li;
pm_addr <= pm_addr_li;
is_stack_almost_full <= to_sl(is_stack_almost_full_ui);
END struct;
--------------------------------------------------------------------------------
--
-- Configuration : cr816_top_cfg
-- Entity : cr816_top
-- Description :
--
--------------------------------------------------------------------------------
CONFIGURATION cr816_top_cfg OF cr816_top IS
FOR struct
END FOR;
END cr816_top_cfg;
Please provide a solution.
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