seeker_123
Member level 2
I am looking for 32 to 40 bit gearbox design at receiver.
Clock frequency at write and read side is same but not from same source.
One is recovered and other is generated at receiver.
Concern is PPM which is +/- 200.
Write side 32 bit input is continuous while read side 40 bit output has one IDLE cycle every 5 cycle. IDLE cycle I can use it for extra word which may be accumulated due to PPM.
Similarly read side i can have one extra idle cycle if FIFO is draining.
How can I design FIFO to handled one extra word or 1 less word because of PPM.
How will i detect when an extra word is accumulated or its draining ?
any guidance on this will be helpful
Clock frequency at write and read side is same but not from same source.
One is recovered and other is generated at receiver.
Concern is PPM which is +/- 200.
Write side 32 bit input is continuous while read side 40 bit output has one IDLE cycle every 5 cycle. IDLE cycle I can use it for extra word which may be accumulated due to PPM.
Similarly read side i can have one extra idle cycle if FIFO is draining.
How can I design FIFO to handled one extra word or 1 less word because of PPM.
How will i detect when an extra word is accumulated or its draining ?
any guidance on this will be helpful