GDS2, SDF, timed simulation of standard cell library

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gezzas525

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My university is trying to sort out the Silicon ensemble and buildgates software packages, the requirement is to do timed simulation of a standard cell library but iam not sure how to do this. Build gates will synthesize the design from vhdl and silicon ensemble will convert the design to gds2. Now I want to do a timed analysis, originally the plan was to use modelsim with an .sdf file format however that would involve writting sdf files for the standard cell library which I have (Virtual Silicon 0.18um Library, UMC).
 

SE can export SDF file for your time analysis also.
 

gezzas525 said:
Now I want to do a timed analysis, originally the plan was to use modelsim with an .sdf file format however that would involve writting sdf files for the standard cell library which I have (Virtual Silicon 0.18um Library, UMC).
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When you do synthesis with BG, you should read the lib to your netlist. Then you can use the command "write_sdf" to write the timing sdf file. Annotate this sdf in your netlist, then do pre-simulation with ModelSim.

After using SE, you can product a sdf file including the wire-delay model. With the same way to do post-simulation.

Certainly, those ways is dynamic timing analysis. You should do STA for complete timing analysis.

Good Luck
 

Thanks I will give these suggestions a go and see what happens.
 

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