gated clock does not active

[nsatheeshyuvaraj]

I am using xilinx ise 9.2i. i wrote simple vhdl code with and without clock gating technique, after the simulation,i had checked power report. the both code consumed same value of power. there is no any changes in power report. what shall i do? if any setting changes are there? any bodies please help me. this is very useful for my project.....

this is my advance thanks.....

 

[morris_mano]

check how often the enable to clock gating is toggling?