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gate voltage of s/h circuit in hold mode

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iamxo

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such as in the MDAC circuit (in pipeline ADC), in sample phase the voltage at opamp input is charged to Vcm, then in the hold phase what is the voltage value at this node? still Vcm?
In my transistor level circuit simulation, in sample phase it's 1.5v, however in hold phase it decreases to 1.43v, how does this happen? anyone help me, thank you in advance.

Or Does any material talk about this?
 

Probably charge injection, the Cgs/Cgd and gate
voltage transition impose a unidirectional charge
impulse when you go to hold (some in sample, too,
but it just scoots back out the now-on channel to the
driving source).

You probably want to size the NMOS and PMOS as
small as possible (so the charge is less, making less
pedestal voltage on the hold cap) and tweak sizes
until you get a first-order cancellation of net charge.
Too small a switch increases sample-mode settling
time, which is the other design bind.

However this may only be good near VCM, otherwise
dV(N) and dV(P) may differ (voltage swing prior to
turnoff, doesn't count but voltage swing after, does;
so at high common-mode offset the N:p cancellation
may degrade a lot). Limiting the switch gate "off"
voltage swing to a small overdrive beyond
min(VCM,VIN) for N, max(VCM,VIN) for P, will also
minimize the charge injection at the cost of some
elaborateness in the gate driver circuitry.
 

Let's say the circuit in the picture, it's a flip-around sample/hold amplifier. In your reply, you mentitoned to size the mos transistor. does it mean to size the mos with the gate controlled by ph1' and ph2 in the uploaded picture?? If it is, then the reduction of mos controlled by ph1' will degrade the SFDR performance of s/h amplifier. So, if you could explain more in detail, i will appreciate you very much.
 

if a smaller switch degrades the SFDR performance, you could try to use a passgate (add a pmos transistor in parallel with the nmos transistors going to Vcm1 and controlled by ph1'_bar). I recommend the pmos to be the same size of the nmos to ease the effect of charge injection.
 

In an NMOS-only scheme as shown you are depending
on the Gm amplifier and circuit symmetry to null the
switch charge skew.
 

JoannesPaulus said:
if a smaller switch degrades the SFDR performance, you could try to use a passgate (add a pmos transistor in parallel with the nmos transistors going to Vcm1 and controlled by ph1'_bar). I recommend the pmos to be the same size of the nmos to ease the effect of charge injection.

I use ideal switch to replace the swith controlled by ph1' which has no paracitic cap,
and find that the gate voltage remains almost Vcm. So, i think this transistor is the cause of voltage variation in the hold phase. However, the On-resistance of pmos swith is much less than nmos. if i use the same switch size of both pmos and nmos, the switch size is quite large. is it OK?? if i just want to use nmos switch, how to reduce the voltage variation??
 

You could attach a replica NMOS connected as a
capacitor, and drive the bottom plate with the opposite
clock phase, sizing this replica for the charge division
you observe in sims.
 

dick_freebird said:
You could attach a replica NMOS connected as a
capacitor, and drive the bottom plate with the opposite
clock phase, sizing this replica for the charge division
you observe in sims.

Although it's a direct way to solve this charge injection problem, i doubt in real circuit whether it is accurate enough not to degrade the opamp settling performance, because after the circuit is fabricated we don't know how much charge will be absorbed by this replica mos.
 

I believe dick_freebird's suggestion works pretty well too! The size should be half off the switch size and my suggestion is that you size them using fingers so that the two transistors "look similar"...
 

JoannesPaulus said:
I believe dick_freebird's suggestion works pretty well too! The size should be half off the switch size and my suggestion is that you size them using fingers so that the two transistors "look similar"...

ok, i have tried the replica swith with half size tied to the charging switch, yes the voltage varies less when it is in the hold phase. However, my settling performance is degraded, which could settle to 20~30uV static error without this dummy swith, while now it just settle to 400uV error.
 

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