Aug 3, 2011 #1 A AutoDriver Newbie level 4 Joined Jun 20, 2011 Messages 5 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,322 When you use Verilog for full chip gate-level simulation, do you use delay on standard cell library? Why? Do you use delay on the test program? When do and when do not? Why?
When you use Verilog for full chip gate-level simulation, do you use delay on standard cell library? Why? Do you use delay on the test program? When do and when do not? Why?
Aug 3, 2011 #2 A atulaxc Member level 1 Joined Jan 25, 2010 Messages 39 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,288 Activity points 1,467 Delays are required on IP/RTL models involved in gate-level sims. These Verilog #delays insert required routing delays on actual (hardware) paths.
Delays are required on IP/RTL models involved in gate-level sims. These Verilog #delays insert required routing delays on actual (hardware) paths.
Aug 5, 2011 #3 L ljxpjpjljx Advanced Member level 3 Joined May 5, 2008 Messages 968 Helped 80 Reputation 162 Reaction score 56 Trophy points 1,308 Location Shang Hai Activity points 4,679 you should specify a file to load all delay!