vlsi_freak
Full Member level 2
fpga gate count
Hi All,
In Fpga's give area report based on number of Slices used by logic.
In Xilinx technology what is the equilant gate count for 1 slice/clb. How can a user predict gate count during FPGA prototyping.
Is slice count same as ALUT count in Altera FPGA.
Please share your thoughts,
regards,
freak
Hi All,
In Fpga's give area report based on number of Slices used by logic.
In Xilinx technology what is the equilant gate count for 1 slice/clb. How can a user predict gate count during FPGA prototyping.
Is slice count same as ALUT count in Altera FPGA.
Please share your thoughts,
regards,
freak