abhinavpr
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Hi,
i am always confused whether to go for combinatorial design or sequential design. there are always tradeoffs between different parameters and area is one of the most important of them all.
can anybody tell me what guidelines to follow while designing rtl to reduce area of the ckt.
we can always get the gate count after synthesis but before that while writing RTL how to figure out which design would be area efficient.
for example while designing a state machine we can go for binary encoding or one hot encoding.
one hot has timing benifits
but what about area?
for a small no. of states arnd 25 which would be more efficient one hot or binary?
one hot will involve 25 ffs and binary will have 6 but binary will also have decoder logic(comb)
in terms of gate count which will be more efficient?
i am always confused whether to go for combinatorial design or sequential design. there are always tradeoffs between different parameters and area is one of the most important of them all.
can anybody tell me what guidelines to follow while designing rtl to reduce area of the ckt.
we can always get the gate count after synthesis but before that while writing RTL how to figure out which design would be area efficient.
for example while designing a state machine we can go for binary encoding or one hot encoding.
one hot has timing benifits
but what about area?
for a small no. of states arnd 25 which would be more efficient one hot or binary?
one hot will involve 25 ffs and binary will have 6 but binary will also have decoder logic(comb)
in terms of gate count which will be more efficient?
