There have been functional bugs.. but nothing that could not have been caught in RTL. It just happened that they were caught late in the verification cycle
here is one:
The design contains a divide by 3 clock divider. the requirement is that clocks must be free running and synchronous. since the divider is free running, resets does not affect the initial state of the flops in the divider circuit, ie in simulation they will be x. So it was required to initialize these flops to some value, ie 0 or 1. When these flops initialized with some random 0 or 1, for a particular combination it was seen that the divider was not giving the desired output.
This could have been caught in RTL as well as the design was in structural coding.