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Min, Max, Typical violation in GLS

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Ben_Beckman

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What are some of the major reasons for causing timing violations while doing gate level simulation?
 

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Ben_Beckman said:
What are some of the major reasons for causing timing violations while doing gate level simulation?
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If the design is over-clocked during GLS, you violate setup time. The hold violations are fixed at the post layout stage. So if not for the first case, you might be seeing hold violations...
 
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