Fully differential OTA design for low power SC integrator

[erikl]

you said : "choose a larger gm/ID value, more in weak inversion, which gives you even better transconductance (gm) efficiency, but will decrease your DC gain because of lower VA (and your UGB)"

This would be correct if you could trust your gm/Id vs. VA curves. But see below:

The gain Av = gm x ro = gm x VA/ID, so with a high gm/ID, the gain decrease, I think it's interressant to work with small gm/ID because of huge VA! So what is the real need to work in weak inversion if we have a little gain?

Thinking twice, I reviewed Binkley's curves on these contexts, and they seem quite different from yours:

VA doesn't drop so much with increasing gm/Id as in your figure. It's from a 180nm process, but anyway ...

Other point, I ran a lot of simulation but a current of 100nA, with the chart I have I can't get a big gm/ID because of a small ID/W/L (the possible values for W and L are between 0.4 and 10µm) but I got a gain of 60dB in the first differential pair (inputs are -6dB)! Unfortunately I can't get this at the output stage! What is weard is that I'm not able to find it with calculation! Both transistors seems to be in weak inversion because ID/W/L = 0.2µ for the PMOS (current mirror) and = 2.5µ for the NMOS. So I'm not able to understand why the gain is so important! Here is the simple schematic with the results

I think your simulation schematic isn't ok:

1. I don't see if your stimuli sources V3 & V4 include any DC voltages. If they don't, you have DC=0V at both inputs. Also, see the *Error* messages at M10 & M12. Check your operation point voltages!

2. Both ac sources seem to stimulate common mode ac voltages. So how could you expect much gain at all?

You need full DC feedback from Vout+ to Vin- and from Vout- to Vin+ (e.g. using 1GΩ feedback resistors plus 1GF caps to GND), inserting a single unit ac source between one of the feedback points and one of the Vin inputs. Cf. my schematic below. Or use SPECTRE's iprobe method.

If I change the input offsets, the gain change also. The current simulation is with a 1Vdc offset, if not, I'm loosing a lots of dBs!

Of course: your sim schematic doesn't use full DC feedback! So it simply moves away from a (perhaps previously) good operation point.

May be this design will not working but if I understand the concept I need a higher biasing current because of the best W/L I can get is 0.04 so in order to have a reasonnable VA I need 20µ so ID= 0.8µA at least.
Am'I right?

Not necessarily. I tried a similar design (single ended only) in weak inversion mode, using W/L=8 for nMOS and W/L=20 for pMOS. Got nearly 60dB DC gain and a UGB≈350kHz with bias currents of 100nA and Cload=100fF. Unfortunately I've got no access to Cādence tools nor to a 90nm lib, but I think my transistors' properties should be close to theirs. See the PDF below!

I forgot to mention: In no way this is a complete, optimized circuit! This is a quick shot I made for the most simple type of a 2-stage Miller-OTA, estimated and calculated for a low-power low-frequency circuit operating at the onset of deep weak inversion mode (IC≈0.01 for 90nm process), not at all optimized for power/speed nor equipped with the Miller cap, which is surely necessary for low gain feedback operation. But IMHO it's a good start point for optimizing such a design.

 

[Fabien]

VA doesn't drop so much with increasing gm/Id as in your figure. It's from a 180nm process, but anyway ...

Maybe you are right. I don't really know hot to plot the Gm/ID vs VA. Here is how I did it:
- first I simulate the gm by increasing Vgs with Vds fixed. I got the Id vs Vgs, in this way I can plot gm/ID vs Vgs.
- secondly I simulate the same transistor with Vgs fixed and increasing Vds. I got ID vs Vds so I can have the VA vs Vds.
once I got these curves, I saved it in a CSV file in order to have gm/ID and VA, so I can plot gm/ID vs VA. Not sure it's a good way but I didn't find any explications. :/

1. I don't see if your stimuli sources V3 & V4 include any DC voltages. If they don't, you have DC=0V at both inputs. Also, see the *Error* messages at M10 & M12.

The V3 and V4 have a phase of 180° with a dc voltage of 1V. The *Error* messages are because I used parametric simulations.

You need full DC feedback from Vout+ to Vin- and from Vout- to Vin+ (e.g. using 1GΩ feedback resistors plus 1GF caps to GND), inserting a single unit ac source between one of the feedback points and one of the Vin inputs. Cf. my schematic below. Or use SPECTRE's iprobe method.

I'm using Eldo, but you'r right, I got better results with a feedback. I tried your design and I got around 50dB gain and 1MHz GBW.

Ok, it's a good point to start. But I'm still wondering how to do it by hand calculation. Did you use some kinds of charts? GM/ID vs VA, vs ID/W/L .. ?

 

[erikl]

I don't really know hot to plot the Gm/ID vs VA. Here is how I did it:
- first I simulate the gm by increasing Vgs with Vds fixed. I got the Id vs Vgs, in this way I can plot gm/ID vs Vgs.
- secondly I simulate the same transistor with Vgs fixed and increasing Vds. I got ID vs Vds so I can have the VA vs Vds.
once I got these curves, I saved it in a CSV file in order to have gm/ID and VA, so I can plot gm/ID vs VA. Not sure it's a good way but I didn't find any explications. :/

I don't think this is the right way: you can't establish a correct dependency between 2 parameters (gm/ID vs VA), if the individual parameters (gm/ID & VA) did not depend on the same independent parameter (one was depending on Vgs, the other one was depending on Vds).

I'm using Eldo, but you'r right, I got better results with a feedback. I tried your design and I got around 50dB gain and 1MHz GBW. Ok, it's a good point to start.

No, forget it: actually this is a very bad design of mine, very sorry indeed! I found out that the first stage had no gain at all (<1), but contributed 90° of phase difference (PD), so there was virtually no phase margin (PM), because the 2^nd stage contributed nearly the same PD. A design change was partly successful (1^st stage's gain»1), but didn't allow for enough PM either. So I decided to use only a single stage OTA - no Miller compensation cap needed, because ther's just one pole.

I got quite a good DC gain > 60dB, and a UGB>1MHz even with a Cload of 1pF. And PM=90°, of course, see the PDF below. All this with a bias current of 30nA, total current consumption 100nA.

View attachment 1-stage_LP_OTA_90nm.pdf

I'm not sure how well my transistors' internal caps match your library transistors' ones, but you could give it a try.

But I'm still wondering how to do it by hand calculation. Did you use some kinds of charts? GM/ID vs VA, vs ID/W/L .. ?

W/L calculation (depending on ID and the inversion mode) after Binkley's book (helping with Excel charts, try it!), and some experience.

Don't forget: for a fully differential OTA you'll need an additional CMFB circuit!

 

[Fabien]

Thanks again for your design!!
Actually I got almost the same results, the differential pair has a gain of less than 0db, but the output stage is 45dB.

I got quite a good DC gain > 60dB, and a UGB>1MHz even with a Cload of 1pF

Once again, almost same rslts, 51dB and 100kHz GBW.

What kind of excel charts did you use? Some equations with parameters such as W, L , ID ... ? I read some parts of the Binkley's book, the gm/ID vs VA seems not to be that simple.

Don't forget: for a fully differential OTA you'll need an additional CMFB circuit!

Sure! Actually, I already design a fully differential folded cascode OpAmp, with a CMFB but the consumption was too high (tens of µA) the CMFB is done with an other single ended op amp witch inputs are sensing the output common mode (resistor ladder) and the CMRR after MC simulation was really bad!
That's why I wanted to design a simple miller OTA but with a methodology that I can use to tune it for low power. I think I'll use SC capacitors for the CMFB or something more low power.

Thank you for your help and this discussion!

- - - Updated - - -

GOT IT!!
I calculate all transistor of this schematic and I got 56db! It's quite similar to the schematic but it take a bit time. Need to know all voltages at the transistors and then simulate each transistor with the corresponding bias voltages and find the gm/ID, the VA and then the formula: Av = gm/ID x VA2.VA4/(VA2 + VA4) . But the results seems to be same as the simulations of the OTA!

tks

 

[erikl]

What kind of excel charts did you use? Some equations with parameters such as W, L , ID ... ?

Actually I didn't use Binkley's MOSFETs Sheets (shown and described in Appendix A of his book). I just extrapolated the technology current for your process (which is the Id for (W/L)=1) from Binkley's 180nm values to be ≈1.3µA (for NMOS), then decided on an Inversion Coefficient (IC) value for near deep weak inversion mode of IC≈0.01 to operate in very low power region, and on relatively long transistor lengths (in relation to your process' minimum length) to get rid of mobility reduction and DIBL effects - and VA reduction - all this possible because of no high frequency operation necessity, and no silicon area restriction - as you allowed for.

I read some parts of the Binkley's book, the gm/ID vs VA seems not to be that simple.

For L ≧ 10*L_min - after Binkley's VA curves - one doesn't have to care about too low VA values, so I didn't give much attention to this.

I think I'll use SC capacitors for the CMFB or something more low power.

For the CMFB amp, also a single stage OTA should do: you could take the very same design as for your actual SC-OTA, but in single ended format of course.

Sure: use only caps between the SC-OTA outputs and the CMFB input. A value a factor of 4 less than your SC feedback caps should do.

GOT IT!!
I calculate all transistor of this schematic and I got 56db! It's quite similar to the schematic but it take a bit time. Need to know all voltages at the transistors and then simulate each transistor with the corresponding bias voltages and find the gm/ID, the VA and then the formula: Av = gm/ID x VA2.VA4/(VA2 + VA4) . But the results seems to be same as the simulations of the OTA!

Congratulations!

Thank you for your help and this discussion!

De rien, Fabien ! Mon plaisir. Bon courage !
erikl