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Fully-controlled single-phase scr bridge rectifier: Rl load

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Barbarawi

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in the last post ::

press down link . to understand the project !

https://www.edaboard.com/thread270615.html

so far everything in the software "ISIS Proteus " working as I need

but in the LAB , when I connected the circuit .. the output is not like the output in the ISIS ..

I could not figure out what's the problem !! :shock: :cry:

this attachment can at least describe the problem !!

error in my output.jpg

is the problem from the type of the SCR thyristor ?!

but if it's the problem why in the half first cycle there's an output !?

so the problem in the next half cycle of the period
 

FvM

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Browsing the said project, I only see snippets, no complete circuit. I don't feel motivated to search links and appended files for something meaningful.

I e.g. don't see how trigger circuit synchronization is managed. Presuming there's a zero crossing detector, that's a popular place where a real circuit might fail due to interferences generated by the load.

You can easily find out yourself by watching the trigger pulses together with the output waveform. Is the unwanted behaviour already present in the trigger pulses, or is it generated by the power circuit?
 

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