Thanks,
The LTspice test fixture of LTC3901 is receiving an idealised SYNC signal, and doesn’t have the sense pins connected. Also, its driven by an open loop simulation, so it cant be used with switched loads, which are needed to test out sync rect operation.
Yes i waited for steady state.
The attached ltspice sim of LTC3901 ("_3")again does not work correctly…the sync rect gates are badly driven in spite of the SYNC signal being of an acceptable form.
Also, at t=1ms, there is a high voltage spike on the drain of the sync rect fets (during full_load to no_load)……this would not be acceptable in a real circuit.
I cannot see it being possible to spend money on even a prototype of this if the sim cant be gotten working…..i think it’s a golden rule that a working sim is meaningless…but if a sim cannot be made to work, then it definitely won’t work on the bench.
Another point is that the LTC3901 model in ltspice doesn’t regulate the CSX+ pins to 11v like it should. Also, the calculations on page 9 of its datasheet lead to a negative value of resistance for RCSX2.
LTC3901
https://www.analog.com/media/en/technical-documentation/data-sheets/3901f.pdf
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The attached version ("_4") has the sync fets being switched properly. This was achieved by idealising the drive voltages, and grouunding all the current sense inputs.
Withouut current sense of course, there are unacceptably large overvoltage spikes on the sync rect fet drains.
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The attached (“_5”) ltspice sim of LTC3901 has the sync rects being switched correctly during heavy load.
However, during full-load-to-no-load, it suffers a massive & damaging voltage spike to the sync fet. This is because the only way I could get the sync fets switching correctly was to divide down the secondary sensed current signal into the LTC3901…(aswell as idealising all the drive voltages) …dividing it down so much that there is large current reversal in light load, resulting in bad voltage spiking to the sync fet.
I suspect the LTC3901 datasheet is dubious anyway……since the datasheet talks about allowing the current to reverse in light load…..whereas this is always bad news in the full bridge topology…because it results in high voltage spikes when the sync fet is turned off when reverse current is flowing through it.
The LTC3901 datasheet page 9 also states that the CSX+ pins are clamped to 11V with a clamp sink that’s “5mA minimum” in capability. This must mean “maximum” not “minimum”.
I am wondering how this part works on the bench? The low 10.5mV sense threshold on the LTC3901 suggests vulnerability to noise problems. And the part cant stop reverse current flowing in the sync fets….or rather it only stops reverse current flowing when its actually already flowing……ie too late….which is going to give potentially damaging voltage spikes on the SRs………Also, the sense threshold is 10.5mV…..so with a 2 milliohm rdson fet, that’s over 5 Amps of reverse current that can flow before it turns off….hmmmm
Does anyone have data of this part working on the bench?