full adder counter in vhdl code

[roomy]

hello
i need help for my code in test bench ..
the code is

use IEEE.STD_LOGIC_1164.ALL;


entity ff_vhdl is
Port(a,b : in std_logic_vector(3 downto 0);
cin : in std_logic;
s: out std_logic_vector(3 downto 0);
cout : out std_logic);
end ff_vhdl;

architecture structural of ff_vhdl is
component adder_vhdl
port (in1,in2,fin: in std_logic;
sum,fout : out std_logic);
end component;
signal c1,c2,c3: std_logic;
begin

ff0: adder_vhdl
port map ( in1=>a(0),in2=> b(0),fin=>cin,sum=>s(0),fout=>c1);
ff1: adder_vhdl
port map ( in1=>a(1),in2=> b(1),fin=>c1,sum=>s(1),fout=>c2);
ff2: adder_vhdl
port map ( in1=>a(2),in2=> b(2),fin=>c2, sum=>s(2),fout=>c3);
ff3: adder_vhdl
port map ( in1=>a(3),in2=> b(3),fin=>c3, sum=>s(3),fout=>cout);

end structural;
i need to creat test bench for this code i try many times and can not able to do it
any help pleas

 

[K-J]

Re: full adder counter i n vhdl code

hello
i need help for my code in test bench ..
<snip>
i need to creat test bench for this code i try many times and can not able to do it
any help pleas

Post the testbench code you have now, many will be happy to help. By posting nothing, you're expecting people to do it all and suggests that you have done nothing.

Kevin Jennings