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I am not sure what you mean by FSM tools.....finite state machines.... it is basically verilog files which you write. Once verified, the RTL compiler(synthesis too) will automatically analyze the FSM state tables( remove the redundant ones) etc and up with optimal FSM state table. It will remove the redundant ones. very small designs can done through manual analysis for rest it is synthesis tools... https://www.amazon.com/FSM-based-Di...F8&qid=1420831209&sr=8-1&keywords=verilog+fsm
You can go over this book if interested....
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